ee457_Final_Fall2004

ee457_Final_Fall2004 - Fall 2004 EE457 Final Exam (35%)...

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ee457_Final_Fall2004.fm 12/8/04 EE457 Final Exam - Fall 2004 1 / 12 C Copyright 2004 Gandhi Puvvada Fall 2004 EE457 Instructor: Gandhi Puvvada Final Exam (35%) Date: 12/10/2004, Friday Closed Book, Closed Notes; Calculators allowed Time: 1:45 - 4:15PM SGM123 Name: Total points: 170 Perfect score: 160 / 170 1 ( 11 + 21 = 33 points) 35 min. -- Note: This is a little difficult design question. Pipelining: Here, we are modifying your lab 7 part 3 as follows. Instead of the SUB3 and the ADD4 units in EX1 and EX2 stages, here we have a SUB3 unit in each of the two execution stages. So the op- erations possible are NOP , SUB3 , and SUB6 (subtract 6 by sub- tracting 3 twice). One-hot coded 2-bit opcode is used as shown below. Instruction Operation Opcode SUB3 SUB6 NOP 0 0 SUB3 $R, $X; ($R) <= ($X) - 3 1 0 SUB6 $R, $X; ($R) <= ($X) - 6 0 1 To execute the SUB3 instruction, you can choose to per- form the subtract 3 operation either in EX1 or in EX2 . You need to exploit this aspect to reduce stalling. For example, in the instruction sequence #1 on the side, you can avoid stalling the dependent SUB3 instruction by postponing the subtraction operation until it reaches EX2 stage. However, in the instruction sequence #2, we avoid- ed stalling the SUB3 but ended up stalling the next SUB6 . This is considered fine. It means, we gain sometimes and we may not gain sometimes. Summary: Our policy for this new design is never to stall SUB3 ; if needed we will execute it in EX2. A SUB6 needs to be stalled if it is dependent on a SUB6 immediately ahead of it or dependent on a SUB3 immediately ahead of it which decided to execute in EX2. All other dependencies can be solved through forwarding. The register file is an internally forwarding register file. 1.1 Given on the next page is a block diagram for this new design. Complete it. 1.2 Also complete on page 3, the postpone logic and the logic for HDU, FU1, and FU2. IF RF EX1 EX2 WB SUB3 ADD4 IF RF EX1 EX2 WB Note Lab 7 Part 3 This new design SUB6 $4, $2; ($4)<=($2)-6 SUB3 $6, $4; ($6)<=($4)-3 SUB6 $4, $2; ($4)<=($2)-6 SUB3 $6, $4; ($6)<=($4)-3 SUB6 $8, $6; ($8)<=($6)-6 Instruction Sequence #1 Instruction Sequence #2 11 pts 21 pts
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ee457_Final_Fall2004.fm 12/8/04 EE457 Final Exam - Fall 2004 2 / 12 C Copyright 2004 Gandhi Puvvada PC XA Reg. File RA RD R-Write 0 1 A Comp Station in RF Stage XMEX1 XMEX2 PP Q IF RF EX1 EX2 WB ID_XA EX1_RA EX2_RA P=Q XMEX1=ID_XA Matched with EX1_RA SUB3 SUB6 XD HDU SUB3_1 SUB3_2 EN A-3 FU1 Write FU2 EX1_SUB3_1 EX1_ PRIORITY RESET 1. Complete all missing connections to the Reg. File. Also complete the RA(Result Addreee) connection in ID stage (ID_RA). 2. Complete all five enable (EN) controls on the pipeline registers. 3. Complete the skip controls(SKIP1,SKIP2). 4. Draw the logic for the postpone logic, HDU, FU1, and FU2 on the next page. EX2_SUB3_1 EX2_ WB_RA WB_Write WB_RD X1_Mux R1_Mux X2_Mux R2_Mux SKIP1 SKIP2 Qualifying signals Signals Modified Lab 3 Part 3 Block Diagram I-MEM EX2_XMEX1 STALL FORW1 FORW2 postpone logic
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ee457_Final_Fall2004.fm 12/8/04 EE457 Final Exam - Fall 2004 3 / 12 C Copyright 2004 Gandhi Puvvada Reproduced below is the logic in RF_stage converting the SUB3 and SUB6 control signals into SUB3_1 and SUB3_2 signals.
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This note was uploaded on 11/02/2008 for the course EE 457 taught by Professor Puvvada during the Fall '08 term at USC.

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ee457_Final_Fall2004 - Fall 2004 EE457 Final Exam (35%)...

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