ee457_Final_su2005

ee457_Final_su2005 - Summer 2005 EE457 Final Exam (35%)...

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ee457_Final_su2005.fm 7/30/05 EE457 Final Exam - Summer 2005 1 / 13 C Copyright 2005 Gandhi Puvvada Summer 2005 EE457 Instructor: Gandhi Puvvada Final Exam (35%) Date: 8/1/2005, Monday Closed Book, Closed Notes; Calculators allowed Time: 9:45 AM- 12:15PM GFS116 Name: Total points: 179 Perfect score: 155 / 179 1 ( 20 points) 15 min. Constant Adder to add SIX: You need to add six (6 10 = 000110 2 ) to a 6-bit number X (X 5 X 4 X 3 X 2 X 1 X 0 ) to produce an 7-bit result Z (Z 6 Z 5 Z 4 Z 3 Z 2 Z 1 Z 0 ). Z0 is already produced. Produce Z 1 and Z 2 using simple heuristic techniques. Also produce C3 (carry 3) to go into the 3- bit incrementer on the left. Recall the incrementer design in your HW#8 and simplify the 3-bit incrementer on the left. Delete either p’s (p 5 p 4 p 3 ) or g’s (g 5 g 4 g 3 ) and write equations to the other (g’s or p’s) and then write equations for C’s (C 6 ,C 5 ,C 4 ). Find the individual delay in gate delays for producing each of the 7 bits of Z (Z 6 Z 5 Z 4 Z 3 Z 2 Z 1 Z 0 ). To produce the sum bit "s" from two single bits "a" and "b", we use an XOR gate: s = a XOR b; Do you use (a XOR b) or (a XNOR b) operation to produce the sum bit "s" from summing "a" and "b" and a "1"? (a XOR b) / (a XNOR b) Please count the delay of an XOR gate or an XNOR gate as two-gate delays. a b cin pg s a b cin s a b cin s p2 g2 p1 g1 p0 g0 c0 c0 c1 c2 CLL a2 a1 a0 S2 S1 S0 c3 GND GND GND X5 X4 X3 X2 X1 X0 Z6 Z5 Z4 Z3 Z2 Z1 Z0 p5 p4 p3 g5 g4 g3 C5 C4 C3 C3 C6 B i t __ gates Z0 __ gates Z2 __ gates Z1 __ gates Z4 __ gates Z3 __ gates Z6 __ gates Z5 in gates Z Delay You deleted ____________ (p’s / g’s). Equations for the remaining p’s / g’s and also the C’s: __ 3 = __ 4 = __ 5 = C4 = C5 = C6 = 0
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ee457_Final_su2005.fm 7/30/05 EE457 Final Exam - Summer 2005 2 / 13 C Copyright 2005 Gandhi Puvvada 2 ( 5 + 2 + 8 = 15 points) 10 min. Non-linear pipeline: 2.1 The ICV (Initial Collision Vector) for a non-linear pipeline is C 4 C 3 C 2 C 1 = 1010. -- Complete the incomplete state diagram on the side, -- find the greedy simple cycles -- and find MAL (Minimum Achievable Latency). Greedy Simple Cycle: (i) { } (ii) { } Average latencies: (i) (ii) MAL = 2.2 Complete the reservation table on the right to evaluate the function Y2. Y2 = X 4 7 - 6 Note that rasing to the power of 4 can be done by squaring twice. Similarly, subtracting 6 can be done by subtracting 3 twice! State-A State-B State-C 1 0 1 0 1 1 1 1 Square Subtract 3 Divide by 7 12345 SQR X Y1 - 3 /7 Reg. Y1 = X 2 - 3 7 Fig. 2.1 Fig. 2.2 Fig. 2.3 2.3 The DPU (datapath unit) on the side was designed to support the evaluation of the functionY1. Y1 = [(X 2 - 3) /7] Design a new DPU below (by adding muxes, etc.) such that the new DPU supports the evaluation of both Y1 function and Y2 function also as defined in question 2.2 above. SQR - 3 /7
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ee457_Final_su2005.fm 7/30/05 EE457 Final Exam - Summer 2005 3 / 13 C Copyright 2005 Gandhi Puvvada 3 ( 23 points) 10 min. Parallel processors: 3.1 There is no ____________ (SISD/SIMD/MISD/MIMD) system. 3.2 Locked-step execution characterizes the behavior of a ___________ (SISD/SIMD/MISD/MIMD) system.
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ee457_Final_su2005 - Summer 2005 EE457 Final Exam (35%)...

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