ee457_Final_Fl2007

ee457_Final_Fl2007 - Fall 2007 EE457 Final Exam (35%)...

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ee457_Final_Fl2007.fm 12/13/07 EE457 Final Exam - Fall 2007 1 / 17 C Copyright 2007 Gandhi Puvvada Fall 2007 EE457 Instructor: Gandhi Puvvada Final Exam (35%) Date: 12/14/2007, Friday Closed Book, Closed Notes; Calculators allowed Time: 8:00 - 10:45AM SGM123 Name: Total points: 257.5 Perfect score: 230 / 257.5 1 ( 65 + 43 + 26 = 134 points) 52 + 30 + 15 = 97 min. New load-word ( lwn ) and store-word ( swn ) instructions with no offset: Mr. Trojan observed (for the sake of this problem) that in most programs, the compiler uses lw (load word) and sw (store word) instructions without any offset (i.e. with zero offset). example: lw $6, 0($2) and sw $8, 0($4) In a very few occasions, compiler uses actual offset values. example: lw $6, 20($2) and sw $8, 20($4) He proposed a new lw instruction lwn ( n for new ) and a new sw instruction swn ) with no offsets. example: lwn $6, ($2) and swn $8, ($4) These new lwn and swn instructions do not need ALU to compute EA ( effective address ) 1.1 Pipeline implementation of the new lwn and swn instructions: Mr. Trojan observed that the lwn and swn with no offsets allow the MEMORY to be brought into the EX stage. This will eliminate extra stalls caused by the old lw instruction. So he decided to combine EX and MEM stages into one stage called EXMEM . However, he did not want to make this new processor incompatible to old binaries. So he decided to support the old lw and sw instructions as well. The old lw and sw instructions will take two clocks in the new EXMEM stage. Your lab 6 5-stage pipeline is shown on the next page. Mr. Trojan’s 4-stage pipeline (partially completed) is shown on page #3. Notice that -- the EX and MEM stages were combined into one stage, called EXMEM . The earlier EX/MEM stage register was removed. However, let us not worry about fixing suffixes for signals such as RegWrite_EX . -- the address to memory can be taken from the output of ALU to support the old lw and sw or it can be taken from the input on A-leg of the ALU (carrying the content of rs register). A new 2-to-1 mux at the address input of the memory facilitates this selection. A new control signal called " Old " is added to the MEM group of control signals. This goes active ( Old = 1 ) when an old lw or an old sw instruction passes through the EXMEM stage. -- a flip-flop hook up (discussed in lab #7) was added to the EXMEM stage to stall the pipeline for one clock when the old lw or the old sw is in EXMEM stage. -- previous STALL signal control is removed from the PC and the ID/EXMEM stage registers. Add all needed STALL arrangements. Old 0 1 D Q CLK Q CLK
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ee457_Final_Fl2007.fm 12/13/07 EE457 Final Exam - Fall 2007 2 / 17 C Copyright 2007 Gandhi Puvvada Hazard detection unit 0 4 Instruction memory PC + r1 r2 R1 R2 w W opcode rs rt rd shift funct Registers Control (PC) (rs) (rt) ALU ctrl Sign ext. EX ME WB ALUSrc ALUOp RegDst RegWrite_EX Data WR ALU_result @ R MemRead MemWrite Store_data RegWrite IF.Flush MEM_data REG_data MemtoReg + = s_ext Shift Left 2 Zero Forwarding Unit Designed by: Gandhi Puvvada Detailed implementation of Early Branch suggested in 3rd Ed. 10/18/06 IF/ID IF-Stage ID/EX ID-Stage EX/MEM EX-Stage MEM-Stage MEM/WB WB-Stage MemRead_EX MemRead_MEM WriteRegister_EX
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This note was uploaded on 11/02/2008 for the course EE 457 taught by Professor Puvvada during the Fall '08 term at USC.

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ee457_Final_Fl2007 - Fall 2007 EE457 Final Exam (35%)...

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