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THE UNIVERSITY OF TEXAS AT DALLAS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING CE/EEDG 6301 Assignment #4 Rohith Reddy Krishnareddi Gari NetID: rxk152130
1. Let Control Gates closed and Red Light flashing be -> Output-1 -> Y1Now, Train in defined section of track -> Input-1 -> D1And, Train passed crossing -> Input-2 -> D2S0: No Train anywhere S1: Train in defined section of track S2: Train in further defined section of track which straddles crossing S3: Train passed crossing D1D2 State 00 01 11 10 S0S0, 0 - - S1, 1 S1 - S3, 0 S2, 1 S2, 1 S2 - S3, 0 S2, 1 S2, 1 S3 S0, 0 S3, 0 - - States S1& S2are basically same so modify the state table by combining them. D1D2 State 00 01 11 10 S0S0, 0 - - S1, 1 S1= S2 - S3, 0 S1, 1 S1, 1 S3 S0, 0 S3, 0 - - Only 1 stable state in each column.
Verilog Code: module rail_cross(input D1, input D2, output reg Y1); parameter S0 = 0 ;//No Train anywhere parameter S1 = 1 ;//Train in defined section of track parameter S2 = 2 ;//Unused state parameter S3 = 3 ;//Train passed crossing reg [1:0] state ; initial state = S0 ; //always @ (D0 or D1 or state) always @ (D1 or D2)

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