cse331-week11_12 - CSE331 W11&12.1 KB Fall 2008...

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Unformatted text preview: CSE331 W11&12.1 KB Fall 2008 PSU CSE 331 Computer Organization and Design Fall 2008 Week 11&12 Section 1& 2 Kabekode V. Bhat: Course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides] CSE331 W11&12.2 KB Fall 2008 PSU Heads Up Last weeks material Designing a MIPS single cycle datapath This weeks material Multicycle MIPS datapath implementation, microprogramming- Reading assignment PH: 5.5, 5.7, B.10, C.3-C.5 Next weeks material Input/Output dealing with exceptions and interrupts- Reading assignment PH: 5.6, 8.1, 8.5, A.7-A.8 CMPEN331 Exam #2: November 10, 2008, 6:30-7:45pm, 119 Osmond CMPEN331 FINAL EXAM Tuesday, Dec 16, 2008, 8:0-9:50am 101 Chamber CSE331 W11&12.3 KB Fall 2008 PSU By the time it is externally visible that things have gone awry, many millions or even billions of clock cycles may have transpired. as you stand there helpless and befuddled in the debug lab, the scales fall from your eyes, and you see clearly and ruefully that during design you should have provided an entire array of debug and monitoring facilities, with enough flexibility to cover all the internal facilities you wish you could observe right now. The Pentium Chronicles , Colwell, pg. 72 CSE331 W11&12.4 KB Fall 2008 PSU Review: Single Cycle Data and Control Path Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 16 32 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control 1 1 1 1 ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Instr[31-26] Branch Shift left 2 1 Jump 28 Instr[25-0] 26 PC+4[31-28] 32 CSE331 W11&12.5 KB Fall 2008 PSU Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently the clock cycle must be timed to accommodate the slowest instr especially problematic for more complex instructions like floating point multiply May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but It is simple and easy to understand Clk lw sw Waste Cycle 1 Cycle 2 CSE331 W11&12.6 KB Fall 2008 PSU Multicycle Implementation Overview Each instruction step takes 1 clock cycle Therefore, an instruction takes more than 1 clock cycle to complete Not every instruction takes the same number of clock cycles to complete Multicycle implementations allow faster clock rates different instructions to take a different number of clock cycles functional units to be used more than once per instruction as long as they are used on different clock cycles, as a result- only need one memory- only need one ALU/adder CSE331 W11&12.7 KB Fall 2008 PSU The Multicycle Datapath A High Level View Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1...
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This note was uploaded on 11/03/2008 for the course CMPEN 331 taught by Professor Bhat during the Fall '08 term at Pennsylvania State University, University Park.

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cse331-week11_12 - CSE331 W11&12.1 KB Fall 2008...

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