cse331-week7_8

cse331-week7_8 - CSE 331 Computer Organization and Design...

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CSE331 KB Fall 2008 PSU CSE 331 Computer Organization and Design Fall 2008 Section 1 & 2 Course material on ANGEL: cms.psu.edu [ Thanks to Mary Jane Irwin adapted from D. Patterson slides ]
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CSE331 KB Fall 2008 PSU Head’s Up Last week’s material Intro to VHDL This week’s material Number representation, basic arithmetic operations, MIPS ALU design - Reading assignment – PH 3.1-3.5, B.5-B.6 Next week’s material Designing a MIPS single cycle data path - Reading assignment – PH 5.1-5.3, B.7 Reminders HW 5, due Monday, OCT 13 (by 11:55pm) Quiz 3, 4, 5 is due Monday, OCT 13 (by 11:55pm) TA to upload correct files on Angel .
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CSE331 KB Fall 2008 PSU Architects write the checks that the design engineers have to cash. If the amount is too high, the whole project goes bankrupt. Design engineers must constantly juggle many conflicting demands: schedule, performance, power dissipation, features, testing, documentation, training and hiring. The Pentium Chronicles , Colwell, pg. 64 & 63
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CSE331 KB Fall 2008 PSU Review: VHDL Supports design, documentation, simulation & verification, and synthesis of hardware Allows integrated design at behavioral and structural levels Basic structure Design entity-architecture descriptions Time-based execution (discrete event simulation) model Design Entity-Architecture == Hardware Component Entity == External Characteristics Architecture (Body ) == Internal Behavior or Structure
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CSE331 KB Fall 2008 PSU Review: Entity-Architecture Features Entity defines externally visible characteristics Ports: channels of communication - signal names for inputs, outputs, clocks, control Generic parameters: define class of components - timing characteristics, size (fan-in), fan-out Architecture defines the internal behavior or structure of the circuit Declaration of internal signals Description of behavior - collection of Concurrent Signal Assignment (CSA) statements (indicated by <= ); can also model temporal behavior with the delay annotation - one or more processes containing CSAs and (sequential) variable assignment statements (indicated by := ) Description of structure - interconnections of components; underlying behavioral models of each component must be specified
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CSE331 KB Fall 2008 PSU Arithmetic Where we've been Abstractions - Instruction Set Architecture (ISA) - Assembly and machine language What's up ahead Implementing the architecture (in VHDL) 32 32 32 m (operation) result A B ALU 4 zero ovf 1 1
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KB Fall 2008 PSU ALU VHDL Representation entity ALU is port( A, B : in std_logic_vector ( 31 downto 0 ); m : in std_logic_vector ( 3 downto 0 ); result : out std_logic_vector ( 31 downto 0 ); zero : out std_logic; ovf : out std_logic) end ALU ; architecture process_behavior of ALU is . . . begin
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cse331-week7_8 - CSE 331 Computer Organization and Design...

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