ps2_solution - 2L . EE 306 FALL loo? PROISLEM SET 1 Sownom...

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Unformatted text preview: 2L . EE 306 FALL loo? PROISLEM SET 1 Sownom of XOR gates can be. used ta) test A 50163 ace, an odd number of is. to problem Star m “HHS PVOMUY‘ Set- /Hso refer NOT(A AND (B 0K0) ‘r-L 3 . KNOWS) M33 C) OR A AL‘IEKNATIVE SOLU‘HON “NOT A) AND KNor 6) ANDC) OK (A firm? (NOT 8) RN]; 0101;» OK (9 PxNID (NOT 3) RN29 Q) 0R (A AND B ANy (NO—r C3) 0K (A AND 3 AND a) fc'qued by Jrauw'na Out flahéistor 9‘14?- This a tr’uth “fable, CCYCul'i", {for Ha 6 Y ‘—' (A AND C) OK (NOTA AND a) 0" CD) A 3-‘(hput OR gate has {'he SQMQ Huck table . H, , AW V A: w m’ffigiifizmam / fig???“ Threext'nPM AND gate- r<-o\ 5 rd («/4 Three, 'mPU‘t 0R Safel gate. Each row can be represented with one 3 input AND gate. The logical equation for this gate level logic circuit is: A’B’C’+A’BC+AB’C+ABC’. 9. A) The output of the circuit when select line S is 0 is equal to the input A, that is for A=l, output is l and for A=0 output is 0. B) If the S switches from O to l, the output depends on the last propagated value of A, i.e. if the previous output was 0 the output is going to stay 0, and if the previous output was 1, the new output is going to be 1. c) This is a storage element, since it stores the value that A had in the moment when S changed from 0 to l. 10. For implementation of a 4-to—1 mux we need to understand what is the 4-to-l mux doing. The idea is that with 2 selection bits we can distinguish 4 different inputs in the multiplexor and by assigning the values to the selection bits we are building a programmable switch that connects output to one of the 4 inputs. The short table for representing this is: Sl S O l O l z 0 A 0 B L c 1 1) If we look at the table more closely, we can see that selection bit 81 makes the choice will one of the signals in the group (A,B) be on the output or a signal from group (C,D). In each of this groups signal SO makes the precise decision which one will be used. This is presented on the figure So, the output values are: SlSOABCDOUT SlSOABCDOUT 0000000 100000T0 0 0 0001i0 10 00010 0 0 00100 10 00101 0 0 001k10 10 0L0111 0001fi000 1001000 0 0 01010 10 01010 0 0 0110+0 10 01101 0001110 1001111 0010001 1010000 00i1.0011 1010010 0010101 1010101 0010111 1010111 0011001 1011000 0011011l1011010 0011101 1011101 H _.‘~ _.‘_. _ ,_.‘_. fl‘o l 1. a) The value of X controls will we do A+B or A+C. If the input of X is 0 then we will add A+B, if it is equal tol we will add A+C. b) What we have is circuit that does only addition, if we want it to do subtraction we need to convert our number B into a 2’5 complement negative number. The way we do it is by taking the inputs for B, invert it, and put it back into C. What we are still missing is the 1 that we need to add to flipped B to make it a 2’3 complement, however we can use X as an input into the Cin bit of the circuit, so we actually added 1 if we are doing subtraction but we add 0 if we are doing addition. The figure of the circuit is: 3‘ O 903 t >_ $1 .. as ca. E x - 12. a) The propagation of mux is three gate delays since the longest path is inverting S bit, doing 8’ AND A, and in the end we have an OR gate. b) The propagation delay for one full adder is 3 gate delays, so for 4 bit adder it is 12. c) we can reduce it to 3 gate delays by grouping the terms ((A and B) and (C and D) ) and E. ._n b) l :43; F1 N W l n O O O O HO HO 0'0 0‘0 9 h—A O O H O elelolololol El c‘c H‘t—‘c clelololc‘ filo OlU '—‘ O elelolo Ololcle 0} o fie} o ,_. O l O‘O t—t‘H .— O >—‘ O‘H _. _‘¢‘_ O _. l l H a clH‘H l O‘OOOOH HOG o»-4 O l ,__t HHH Lid J H0 °l~|~ l r—‘h—ir—4 Ht—‘OOO ._. ._.. ,__. l ._‘ l >--4 H‘H r—i #H‘H H HHH‘M‘Q elole Olelolelo ._.t ,_; _; b) All the combinations that give the output 1 have an odd number of Is and all the combinations that give output 0 have an even number of Is. ...
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ps2_solution - 2L . EE 306 FALL loo? PROISLEM SET 1 Sownom...

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