Lab_Project1.docx

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ECE-C302 Lab Project #1 Prelab- Due Wed Week 1 in the beginning of class (i) Write down the truth table of the Half Subtractor X Y D B (ii) Write down the Boolean expressions for Difference and Borrow (iii) Draw the circuit for the Half Subtractor made up of basic gates naming all ports/signals (iv) Write down the truth table of the Full Subtractor X Y BIN D BOUT (v) Write down the Boolean expressions for D and BOUT using minterms and simplify as much as possible
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(vi) Draw the circuit of the Full Subtractor in terms of basic gates naming all ports/signals Prelab ( 7 points) initials ____________ Date______________ Time________________ Lab 1A (using Modelsim) – Due Wed Week 1 end of class First do the provided Modelsim Tutorial and make sure you thoroughly understand the different steps involved Tutorial (No credit)
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initials ____________ Date______________ Time________________ Next write VHDL description in all 3 styles for Half Subtractor and Full Subtractor. Entity should be common and architectures should be different. Simulate them and show correct operation for all inputs Half Subtractor ( 3 points ) initials ____________ Date______________ Time________________ (behavioral) initials ____________ Date______________ Time________________
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