L6.Caches_II_2pp

L6.Caches_II_2pp - ECE4750/CS4420 Computer Architecture L6...

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1 ECE4750/CS4420 Computer Architecture L6: Advanced Memory Hierarchy Edward Suh C omputer S ystems L aboratory [email protected] 2 Announcements Lab 1 due today Reading: Chapter 5.1 5.3 ECE4750/CS4420 — Computer Architecture, Fall 2008
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2 3 Overview How to improve cache performance Recent research: Flash cache ECE4750/CS4420 — Computer Architecture, Fall 2008 4 Improving Cache Performance ECE4750/CS4420 — Computer Architecture, Fall 2008 Average memory access time = Hit time + Miss rate x Miss penalty To improve performance:
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3 5 Small, Simple Caches On many machines today the cache access sets the cycle time Hit time is therefore important beyond its effect on AMAT ECE4750/CS4420 — Computer Architecture, Fall 2008 = hit data tag index byte = data tag index byte = mux hit 6 Way Predicting Caches (MIPS R10000 L2) Use processor address to index into way prediction table Look in predicted way at given index, then: ECE4750/CS4420 — Computer Architecture, Fall 2008
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4 7 Improving Cache Performance Decrease Hit Time Decrease Miss Rate Decrease Miss Penalty ECE4750/CS4420 — Computer Architecture, Fall 2008 8 Causes for Cache Misses Compulsory: first-reference to a block a.k.a. cold start misses - misses that would occur even with Capacity: cache is too small to hold all data needed by the program - misses that would occur even under Conflict: misses that occur because of collisions due to block-placement strategy - misses that would not occur with ECE4750/CS4420 — Computer Architecture, Fall 2008
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5 9 Effect of Cache Parameters Larger cache size Higher associativity Larger block size ECE4750/CS4420 — Computer Architecture, Fall 2008 10 Victim Cache (HP7200) ECE4750/CS4420 — Computer Architecture, Fall 2008 L1 Data Cache Unified L2 Cache RF CPU Victim cache is a small asociative back-up cache, added to a direct mapped cache, which holds recently evicted blocks
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6 11 Prefetching Speculate on future instruction and data accesses and fetch them into cache(s) Varieties of prefetching Hardware prefetching Software prefetching Mixed schemes What types of misses does prefetching affect? ECE4750/CS4420 — Computer Architecture, Fall 2008 12 Issues in Prefetching Usefulness Timeliness Cache and bandwidth pollution ECE4750/CS4420 — Computer Architecture, Fall 2008 L1 Data L1 Instruction Unified L2 Cache RF CPU Prefetched data
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7 13 Hardware Instruction Prefetch Alpha 21064 ECE4750/CS4420 — Computer Architecture, Fall 2008 L1 Instruction Unified L2 Cache RF CPU Stream Buffer Prefetched instruction block Req block Req block 14 Hardware Data Prefetching Prefetch-on-miss : One Block Lookahead (OBL) scheme Strided prefetch ECE4750/CS4420 — Computer Architecture, Fall 2008
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This note was uploaded on 11/06/2008 for the course ECE 4750 taught by Professor Suh during the Fall '07 term at Cornell.

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L6.Caches_II_2pp - ECE4750/CS4420 Computer Architecture L6...

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