ece2201_a08_exam2_solution

ece2201_a08_exam2_solution - NAME 50w 170w ECE Box 31le Ma...

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Unformatted text preview: NAME 50w 170w ECE Box # 31le Ma» 72- 8 Miolw 80‘ 5/ Problem Score Points 6.9 . 1% i I_?>._a~ g 3 39.8 25 4 90H 25 5 [L3 20 [73.8 ECE 2201 Term A 2008 -——~ Microelectronics I Exam 2 0 Show all work. DO NOT leave a problem blank. Partial credit may be given. 0 When in doubt, let common sense prevail. Don’t get entangled in unnecessary algebra. 0 As in real life, problems may include more information than required. 0 You will have 50 minutes to complete this exam. 0 NOTE: ALL ANSWERS MUST CONTAIN UNITS!! 0 NOTE: ALL ANSWERS MUST BE CLEARLY MARKEDI! 0 NOTE: BUDGET YOUR TIME! ECE 220] Bitar 1. Basic MOSFET Operation |15| For each of the following circuits, identify the type of MOSFET (N or P Channel) and determine the operating region (triode, saturation or cut-off). Assume that |th is IV for each: a) Type: _N__~_. __SAJ:___ Operating Region: A < I: S b) Type: 4v if? T1 vgiszv Operating Region: T T _‘ (Va-Vt“): 3 v > V05: a, C) Type: ovj-E—a—ij T1 V2j+ Operating Region: 5v :— T f V65 :ov I OFF (0 Type: Operating Region: V2 * jw Operating Region: ECE 220] Bitar 2. NMOS Inverter Operation |15| Figure 2-1 shows an NMOS inverter with a resistive load. The input to the circuit is a 0 to 5V square wave and the supply voltage VDD is 5V. The MOSFET parameters are also given. VDD 5V V, = 1V RD : = 2 10m k ”(W/L) 2mA/V 3 5(4) (10th Armrmu 'Agsu/vuf 17W”: lea/av 1kHz 5v 0 CH‘EOK V0; V4441; 61.7mt/<<(b"-I) YES- 71109(. W/ 1: Figure 2— 1 a) Determine the drain current ID and the drain-to—source voltage VDS when the input signal [10] FM» (‘05:! ( H — (as: n/(w/QNWVQ _ (QM/v1\(5"\ r», -.- one. 5’” ° ID: 61/ lokxz many“:- ”(3'81” Tod VOLT. DIVDDm lag/L :V05 V05 : 6":;K)w : (may b) Is this an ideal inverter? Explain. [5] . (”0. 1H): “Mauve ., Kfllsanv “POLL’JZ‘gQfl” RES/HIM Att' Mic—muz— Jls moo WW M a! On: I vJMLr W fit; all?“ AI & , WM ECE 220] Bitar 3. Extracting MOSFET Parameters |25| Figure 3-1 shows a N-Channel Enhancement Mode MOSFET being used in a particular circuit, along with a family of v-i curves measured at different V03 levels for the device. Based on these curves, answer the following questions. NOTE: The threshold voltage Vt for this MOSFET is 4.0V. 100 ’7 l A ‘0 -----EH---- W0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0[10.0\ A tip; VDSM Figure 3-1 a. If V03 = 10V, determine the drain current ID and the drain-to-source voltage VDS using a graphical technique. What operating region is the MOSFET in at this VGs level? [9] LOAD Lwt ’. wig] //4 I$c= V33- Job S'DM: RD (MIL . um owl: (mount; CUM: Ar poiwsmp_ Vos“V r9 3 elf/ml b. What is the turn-on resistance rDs of this MOSFET at VGs = 10V? [6] lv = (”5 :I‘o ' 75.4 : 933'“ ms 93.252. (you; H 90%, or T/wom 7!) Mr cm. NOT‘ at (0495“,; //’2- d ECE 220] Bitar c. If rDs = 509 at VGS = 7V, determine a value for the process parameter k ’"(W/L) for this MOSFET. (Vé : w) [5] , "’"(W/“=g.,5w/pz d. For the circuit of Figure 3-1, if VGS is reduced to 6V, what is the new drain current ID and drain-to-source voltage VDS? Also, what operating region is the device in? [5] Rama (,vo an; n .9an 1:9 er, WM Vos’x 675V ECE 2201 Bitar 4. CMOS Inverter and Propagation Delays |25| Figure 4-1 shows a CMOS logic inverter driving a capacitive load of IOOpF, and being controlled by a digital input signal Vin switching between 0 and 5V. Several parameters are also given for each MOSFET, and the supply voltage is 5V. NOTE: The process parameters for the devices are NOT equal! +11 5v + M11 W ”” _ wp = 50pm Maggt— (- Lp = lOum w" 959 I k’p = 85uA / v2 _ _ - 7+ IV.p| = 1.0V ‘( Edi/oer Vin 1 + M2: N-Channel . r . "' Vout Wn = 50pm J: _ Ln = lOum ”5 kg: 160uA / v2 n. __ - Figure 4-1 Vm = 1-0" "r a) Determine the propagation delays tPLH (low-to-high output transition) and tin“ (high-to- low output transition) for this CMOS inverter. Please indicate any assumptions that apply. [12] - 05144. no swim» moon '- I l .. : —‘_——-;— 1: {8? ngP “ ((910%) (VSG'll/tJ) CgYM/V§(7:)(fll) D!)- l I 1 *- 3/02, 52n- Kt’fl'flflvwl/e) Qo’w/n] (9)6“— D /——- ' Fez n+1: lot/W 1' m mu) tog“ ~, '5ch $5— Fosp cAa: (:?K.lSL>(/wopp3(425 :1 4/o.{m ipfiL CE.“ P135,L CA; 1 (3 AD. {3% (430.05) A; : OHM“: MW“? 8004 flooCL— ECE 220] Bitar 3. Continued... / b) Using the input signal shown below, CAREFULLY sketch the output voltage V0“, as a function of time on the same graph. Be sure to indicate the propagation delays calculated in part (a). NOTE: Sketch what you would actually see on an oscilloscope and draw your sketch T 0 SCALE! [8] VIN +5V 2.9 ollflm {lo-QM I A/om: OUTPUT ls law/name. c) One desirable feature of a CMOS inverter is to have equal propagation delays. Assuming that the channel length of each device is fixed, what new width should the PMOS device have, in order to achieve this result? [5] w - Km, __ joowvb’bl ( F ’ “T ‘14] * S7) :7 ,1.) ”P a Kai/MB m) 9‘] m SAuwv 0.45524 - §/-wa 8‘ 3’65“” “ " Atom" Dbuax ECE 2201 Bitar 5. CMOS Logic Gate |20| The circuit shown in Figure 5—1 is a CMOS logic gate of some type. +5V M4 j M1 11W Figure 5—1 a) Fill it the table below showing the state of each MOSFET (ON or OFF) and the output voltage for each combination of input states. [10] '\‘ COULD 5F- Ea MIL b) If 0V represents a logic low, and +5V represents a logic high, what is the logic gate function of this circuit? [2] Logical Function = AZ A fl 0 ECE 2201 Bitar c) If r133n = rDsp = 5009 for these MOSFETS, determine the output resistance Rom for each combination of inputs (ie. Rom is the total resistance connected between VDD and the load or between the load and GROUND, depending on the state of the MOSFET switches). [8] goo 57. ...
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