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Unformatted text preview: w , x , and y are connected to the select lines, S 2 , S 1 , S , respectively: f(w, x, y, z) = m(1, 2, 4, 5, 8, 10, 11, 15). 4) Construct a 16:1 MUX using only 2:1 MUXes. 5) Is a 2:1 MUX a complete logic set? Explain. 6) Implement the following function using NAND NAND logic: f = AB + AC + BC + CD + AD, assuming maximum 4-input gates. The resulting circuit should have 3 gate delays....
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This note was uploaded on 11/20/2008 for the course ELEG 2903 taught by Professor Smith during the Fall '08 term at Arkansas.
- Fall '08