ee357_hw7_sol

ee357_hw7_sol - EE 357 Homework 7 Solutions Note: Attach...

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EE 357 Homework 7 Solutions Note: Attach all work to receive full credit 1.) An M68000 based system (with address bus A[23:1]) is designed with a total of 64KB of RAM broken into 4 banks. 64KB memory => 16 address bits, A[15:0] a.) Which address bits will be used to connect to each memory chip? Each 8KB memory gets 13 address bits A[15:3]. b.) Which address bits will be used for bank selection? A[2:1] will select each bank. c.) Which address bits will be used for chip select logic? A[23:16] will be used for chip selection, assuming full address decoding. 2.) A processor has a 28-bit memory address space (i.e. 28-bit addresses). The memory is broken into blocks of 64 bytes each (you need to convert to words). The computer also has a cache capable of storing 16K bytes . a.) How many blocks does the main memory contain? 2 28 bytes / 2 6 bytes per block = 2 22 blocks = 4M blocks b.) How many blocks can the cache store? 2 14 bytes / 2 6 bytes per block = 2 8 blocks = 256 blocks c.) Assuming the cache uses direct-mapping , how many bits are there in each of the TAG, BLOCK, and WORD fields of the address. Show your calculations. 64 bytes per block = 32 words per block => 5 address bits for WORD field, A[5:1] 256 cache blocks => 8 address bits for BLOCK field, A[13:6] We know intuitively that the remaining 14 bits, A[27:14], should make up the TAG field; however, you can check this by taking 2 22 memory blocks / 2 8 cache blocks = 2 14 memory blocks per cache block => 14 bits for the TAG field. d.)
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ee357_hw7_sol - EE 357 Homework 7 Solutions Note: Attach...

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