EE200_Weber_11-4

# EE200_Weber_11-4 - Example: A simple IIR filter The left...

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43 EE 200 Signal Flow Graphs The architecture of digital filter can be represented graphically using a block diagram consisting of delays, multipliers and adders. A unit delay is indicated by a box and in most cases we strings several of these together to form a delay line . Taps on the output of each delay element allows us to obtain the value in the line at that point. D D D D D D D D

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44 EE 200 Signal Flow Graphs Example: A simple FIR filter Multiplication operations are indicated by triangles, addition by circles. D + D + D + D + h(0) h(1) h(2) h(3) h(L-1) y(n) x(n) x(n-1) x(n-2) x(n-3) x(n-L+1) y ( n ) = h ( k ) x ( n " k ) k = 0 L " 1 # = h (0) x ( n ) + h (1) x ( n " 1) + h (2) x ( n " 2) + L + h ( L " 1) x ( n " L + 1)
45 EE 200 Signal Flow Graphs We can draw the signal flow diagram for a FIR filter in multiple ways. D + D h(0) h(1) h(2) h(L-1) y(n) x(n) x(n-1) x(n-2) x(n-L+1) + D +

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46 EE 200 Signal Flow Graphs
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Unformatted text preview: Example: A simple IIR filter The left part is identical to an FIR filter with the b(k) weights. The right part is a similar structure but with the y(n) value being fed into the delay line and the a(k) values multiplying past values of y(n). y ( n ) = x ( n " k ) k = L " 1 # b ( k ) + y ( n " k ) k = 1 M " 1 # a ( k ) = b (0) x ( n ) + b (1) x ( n " 1) + b (2) x ( n " 2) + L + b ( L " 1) x ( n " L + 1) + a (1) y ( n " 1) + a (2) y ( n " 2) + L + a ( M " 1) y ( n " M + 1) 47 EE 200 Signal Flow Graphs Example: A simple IIR filter D + D b(0) b(1) b(2) b(L-1) y(n) x(n) x(n-1) x(n-2) x(n-L+1) + D + + + + D D D a(1) a(2) a(M-1) y(n-1) y(n-2) y(n-M+1)...
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## This note was uploaded on 12/03/2008 for the course EE 200 taught by Professor Zadeh during the Fall '08 term at USC.

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EE200_Weber_11-4 - Example: A simple IIR filter The left...

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