This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: the Carry flag. (rD) ← (rA)[ 0] (rD)[1:31] ← (rA)[0:30] MSR[C] ← (rA) Shift Right Logical: Shifts logically the contents of register rA, one bit to the right, and places the result in rD. A zero is shifted in the shift chain and placed in the most significant bit of rD. The least significant bit coming out of the shift chain is placed in the Carry flag. (rD) ← 0 (rD)[1:31] ← (rA)[0:30] MSR[C] ← (rA)...
View Full Document
- Fall '07
- Microprocessor, SEPTA Regional Rail, Most significant bit, one bit, significant bit