Automatic_Synthesis_of_Digital_Circuits.pdf

Automatic_Synthesis_of_Digital_Circuits.pdf - VLSI Design I...

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Unformatted text preview: VLSI Design I Automatic Synthesis of Digital Circuits Why should I not enjoy life instead of drawing schematics if CAD tools can do the job for me? Š Overview design abstraction domains architectural models Š Goal: You are familiar with the design abstraction domains, the descriptiondescription-synthesis design method, the design strategies as well as the three synthesis steps. You know the FSMD architectural model as well as the interprocess communication models. MicroLab, VLSI-22 (1/40) JMM v1.4 Introduction system complexity is increasing ‹ product lifetime is decreasing Ö design efficiency is essential Ö new design methods are necessary Ö higher abstraction levels are introduced Ö CAD tools able to handle large amounts of data are needed ‹ MicroLab, VLSI-22 (2/40) JMM v1.4 Design Methodology Š budget ($, speed, area, power, schedule, risk) Š lowlow-level building blocks, highhigh-level architecture Š specification spice paper & pencil Gee, I skipped these steps when doing the project! Š behavioural design, verification Š logic design, verification Š layout, verification schematics simulation timing analysis layout, drc extraction net compare LVS (layout vs schematic) MicroLab, VLSI-22 (3/40) JMM v1.4 Capture--Simulation Method Capture bottom--up approach Š bottom Š structure of a system is described Š knowledge of an experienced designer is difficult to automate & D Q CLK data clk 3A ena MicroLab, VLSI-22 (4/40) JMM v1.4 Description--Synthesis Method Description Š Š Š Š toptop-down approach behaviour of a system is described technology independent CAD algorithms can search the solution space very quickly & if data-ready then bus := data; else bus := high-Z; end if; D Q clk MicroLab, VLSI-22 (5/40) JMM v1.4 Design methods for VLSI circuits Š use advantages of toptop-down and bottombottom-up design methods Š automatic optimisations are not always ideal, but Š an optimisation of a 70’000 gate design on a 100’000 gate gategate-array makes no sense need of abstract design languages Öneed need to keep the design cycle short Öneed what it is now toptop-down or bottombottom-up ? MicroLab, VLSI-22 (6/40) JMM v1.4 Abstraction Domains Š VLSI designs can be performed in 3 abstraction domains: Š behavioural domain Š structural domain Š physical domain Š each domain gives different freedoms to the designer Š parallel or serial algorithms Š logic technology and bitbit-slice Š fullfull-custom and macromacro-cells ... MicroLab, VLSI-22 (7/40) JMM v1.4 Abstraction Domains: YY--Chart synthesis Behavioural Domain Structural Domain applications, algorithm s processors progra ms system AL Us, registers subro utines, b. equ ations abstraction level instructionslogic gates tra nsistors micro architecture abstraction level logic abstraction level layout, transistors cells chips, mo d ules circuit chips, MC M s, boar ds abstraction level Physical Domain MicroLab, VLSI-22 (8/40) JMM v1.4 Behavioural Domain Š Š Š Š description and verification of first ideas function and not implementation is asked modelling with general purpose languages modula-2, pascal, pascal, c, c++, lisp, ... Š modulamatlab, mathematica, mathematica, ... Š matlab, vhdl, verilogverilog-hdl, hdl, cathedral, ... Š vhdl, vee, ... Š graphic languages as vee, transformation to structural domain: synthesis Behavioural Domain progr a ms subro utines, b. equ ations instructions MicroLab, VLSI-22 (9/40) JMM v1.4 Structural Domain Š Š Š Š description and verification of a solution implementation decisions taken restrictions like delay, signal strength, etc. modelling styles vhdl, verilogverilog-hdl, hdl, Š vhdl, Š schematic Š transformation to physical domain: logic minimization, place and route tools logic Structural Domain processors AL Us, registers logic gates tra nsistors MicroLab, VLSI-22 (10/40) JMM v1.4 Physical Domain Š description and verification of physical implementation Š process technology specific implementation Š floorplan, floorplan, maskmask-layout, packaging Š description formats cif,, gds2 Š cif Š stick diagrams, symbolic layout layout, transistors cells chips, mo d ules chips, MC M s, boar ds Physical Domain MicroLab, VLSI-22 (11/40) JMM v1.4 Abstraction Levels design domains are divided in several abstraction design levels: Š system level Š micro architecture level Š logic level Š circuit level MicroLab, VLSI-22 (12/40) JMM v1.4 Abstraction: System Level Š highest abstraction level Š description with HDLs or graphical block diagrams 64 bit RISC 24 bit graphic accelerator 64 MByte memory 8 GByte hard disk video interface ISDN interface MicroLab, VLSI-22 (13/40) JMM v1.4 Abstraction: Microarchitecture Level Š register transfer system is a pure sequential machine Š use of memory elements and combinational logic Š register transfer is a complete specification on what a chip will do on every cycle output input reg reg combinational logic combinational logic reg combinational logic MicroLab, VLSI-22 (14/40) JMM v1.4 Abstraction: Logic Level Š circuit description on a quite low abstraction level Š today only used to design optimised functional blocks cin sel a b mux s ALU cout MicroLab, VLSI-22 (15/40) JMM v1.4 Abstraction: Circuit Level Š lowest abstraction level Š transistor schematic or maskmask-layout Š comparable to machine code in computer science c a y c b c MicroLab, VLSI-22 (16/40) JMM v1.4 Design Strategies Š the goal is a fast as possible transfer of an idea to a chip Š descriptions in the 3 abstraction domains Š strategies used: Š Š Š Š hierarchy regularity modularity locality a strategy? why not adad-hoc MicroLab, VLSI-22 (17/40) JMM v1.4 Design Strategies: Hierarchy basic idea: divide and conquer Š dividing in modules, subsub-modules until complexity of subsub-modules is comprehensible Š comparison to software engineering: split programs in modules, procedures, subroutines. cin a b adder sum cout cin a b sum cout MicroLab, VLSI-22 (18/40) JMM v1.4 Design Strategy: Regularity Ö goal is reduction of complexity Ö idea: divide in similar building blocks Š identical blocks, subsub-blocks, cells, transistor sizes Š 1-dim. arrays: bitbit-slice technique Š 2-dim. arrays: systolic arrays si+3 ci+3 si+2 full adder ai+3 bi+3 ci+2 si+1 full adder ai+2 bi+2 ci+1 si full adder ai+1 bi+1 ci full adder ai MicroLab, VLSI-22 (19/40) JMM v1.4 bi ci-1 Design Strategies: Modularity different modules should not influence each other Ödifferent subÖsub sub-modules with well formed interfaces: Š do not use transmission gates Š well defined signal types and strengths Š well defined interconnection widths, etc. MicroLab, VLSI-22 (20/40) JMM v1.4 Design Strategies: Locality idea: reduction of complexity due to information Öidea: hiding Š few global variables inter-module influences Š reduction of interŠ reduction of global wiring Š time locality leads to synchron designs (compare local variables in software engineering) I can’t see anything MicroLab, VLSI-22 (21/40) JMM v1.4 Automatic Synthesis /1 Š automatic synthesis: transformation of a design from behavioural to structural domain Š silicon compilation: transformation from behavioural to physical domain synthesis Behavioural Domain Structural Domain silicon compilation Physical Domain MicroLab, VLSI-22 (22/40) JMM v1.4 Automatic Synthesis /2 Š automatic synthesis tools on high abstraction levels do not exist yet Š not every description is synthesizable Š synthesis is a design process and not a only a coding as in software engineering Š synthesis steps: Š allocation Š scheduling Š binding MicroLab, VLSI-22 (23/40) JMM v1.4 Automatic Synthesis: Allocation Š allocation defines the necessary resources Š clocking strategy, pipelining, memory structure etc. have to be defined Š manual allocation reduces the search space of design solutions Š tradetrade-off between chipchip-area and performance Š parallel implementations of designs have high throughput, but consume large areas delay s1 s4 s6 s8 s10 s14 s18 s22 area MicroLab, VLSI-22 (24/40) JMM v1.4 Allocation: Example Š RTL example xx = a + b; yy = a * c; zz = x + d; xx = y - d; xx = x + c; Š allocation: 1 adder, 1 multiplier, 1 substractor a c b + y d + * z x2 + x3 MicroLab, VLSI-22 (25/40) JMM v1.4 Automatic Synthesis: Scheduling Š scheduling defines the operation sequencing Š operations are bound to clock cycles Š scheduling principles: Š resource limited: given a set of resources, solutions for a minimal execution time has to be found time-limited: given a total execution time, a minimal set Š timeof resources has to be found MicroLab, VLSI-22 (26/40) JMM v1.4 Scheduling: Example Š resource limited scheduling Š each operation is bound to a clock cycle Š solutions for minimal execution time Š directed acyclic graphs can be used a cycle 1 cycle 2 cycle 3 c b + y * d - + x2 z + x3 MicroLab, VLSI-22 (27/40) JMM v1.4 Automatic Synthesis: Binding Š binding phase: operations and memory accesses within the clock cycles are bound to the hardware resources Š resources can be reused in different clock cycles Š binding steps: Š variables are bound to memory elements Š operations are bound to functional blocks Š interconnection elements are bound for data transfers (busses, multiplexers) multiplexers) MicroLab, VLSI-22 (28/40) JMM v1.4 Binding: Example Š variables are bound to memories Š temporary variables x1 and x2 are not used simultaneously b cycle 1 a c d + * x1 cycle 2 y + x2 z cycle 3 + x3 MicroLab, VLSI-22 (29/40) JMM v1.4 cont.. Binding: Example cont c x1 x2 reg a mux b mult d y reg reg mux reg reg mux add sub z, x1, x3 x2 MicroLab, VLSI-22 (30/40) JMM v1.4 Architecture Models Š synthesis is based on the knowledge of a set of architecture models and design styles Š design styles: Š parallel or serial datapath Š interrupt or polling control Š memory access types (cache ...) MicroLab, VLSI-22 (31/40) JMM v1.4 Architecture Models: Microarchitecture microarchitecture components microarchitecture Š functional units Š adder, multiplier, comparator, ALU, etc. Š memory elements flip-flop, register, registerregister-file, RAM, ROM ... Š latch, flip- Š interconnection units Š bus, multiplexer MicroLab, VLSI-22 (32/40) JMM v1.4 Architectural Models: Combinational Logic combinational logic: Š non subdividable units carry-lookahead adder ... Š encoder, decoder, carry- Š subdividable units ripple-carry adder, selector, ALUs, ALUs, ... Š ripple- implementation forms Š ROM (table lookup) Š PLA structures (2 stage logic) Š multistage logic Š bitbit-slice, systolic array, etc MicroLab, VLSI-22 (33/40) JMM v1.4 Architectural Models: Finit State Machines finit state machines (FSM) are classical control structures Š autonomous FSM Š no inputs (image processing, ...) Š nonnon-autonomous FSM with inputs (general purpose) Š Mealy machine (general) Š Moore machine (restricted) Š Medwedjew machine (hazard free) MicroLab, VLSI-22 (34/40) JMM v1.4 Architectural Models: Control Unit / Data Path Š FSMs are used for control unit tasks Š datapaths are used as functional units control unit - datapath model (FSMD model) Öcontrol control inputs datapath FSM datapath transfer logic transfer logic status datapath control state register control outputs functional unit datapath MicroLab, VLSI-22 (35/40) JMM v1.4 inputs outputs Architectural Models: System Architecture Š Š Š Š FSMD is used as process on system level system consists of a set of processes hierarchical FSMD model process synchronization is needed process 1 D Q control inputs databus FSM datapath transfer logic transfer logic functional unit datapath control state register clock1 status control outputs D Q control inputs FSM datapath transfer transfer logic logic clock2 transfer logic status datapath control state register control outputs functional unit process 2 MicroLab, VLSI-22 (36/40) JMM v1.4 Architectural Models: Interprocess Communication Š synchronous or asynchronous communications Š no protocol, delay known Š handshake protocol process 1 request aknowledge data data valid process 2 MicroLab, VLSI-22 (37/40) JMM v1.4 Architectural Models: Implementation Constraints Š behavioural modelling uses abstract models, which do not model the reality precisely Ö implementation constraints / pitfalls Š deactivation of set and reset of latches simultaneously Š clock skew in shift registers lead to races of clock and data (two phase clocking strategy) Š Moore and Mealy FSMs have hazards Š asynchronous inputs lead to undefined FSM states Ö never use: Š gated clocks Š combinatorial outputs for asynchronous inputs Š asynchronous inputs as FSM inputs MicroLab, VLSI-22 (38/40) JMM v1.4 Conclusions description--synthesis method Š description Š system design with HDLs (parallel constructions, RTL level) Š toptop-down and bottombottom-up design Š abstract models are not precise Š races, hazards, delays, signal strength, ... Š silicon compiler does not exist MicroLab, VLSI-22 (39/40) JMM v1.4 Coming Up... Next time... Hardware description languages Reading Weste: ‹ Sections 6 thru 6.2.7 (design strategy) ‹ 6.4 thru 6.4.5 (design methods) ‹ 6.5 thru 6.5.4 ((design capture tools) Self study Weste: Weste: ‹ 6.6 thru 6.6.8 (design verification) ‹ 6.8 thru 6.9 (data sheets) MicroLab, VLSI-22 (40/40) JMM v1.4 ...
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