defense.ppt - A Comprehensive Look at VLSI Fault Diagnosis...

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A Comprehensive Look at A Comprehensive Look at VLSI Fault Diagnosis VLSI Fault Diagnosis David B. Lavo Dissertation Defense July 19, 2002
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Outline Outline Background & Philosophy Three-Stage Fault Diagnosis IDDQ Fault Diagnosis Small Fault Dictionaries Conclusions and Future Work
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Format of This Talk Format of This Talk Prior art is introduced throughout Innovations are presented as: Problem to be solved My approach Brief exposition: Background and prior art Particulars and importance of innovations
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Format Example Format Example Problem: This presentation is too long 6 conference papers, 5 years of work, 73 slides Solution: TalkKompress ® technology Rapid delivery High gloss finish Drill-down capability
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VLSI Test (In One Slide) VLSI Test (In One Slide) 1 0 1 1 0 1 0 0 0 1 1 1 1 1 0 0 Fail! Fail! Test Pattern (Vector) Test Response Fault Signature: 1: 5, 6 Test No. Failing Outputs IDDQ Test: Pass: Low Current Fail: High Current
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VLSI Fault Diagnosis VLSI Fault Diagnosis (in One Slide) (in One Slide) Tests Observed Behavior Defective Circuit Diagnosis Diagnosis Algorithm Physical Analysis Location or Fault
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Traditional Fault Diagnosis Traditional Fault Diagnosis Tests Defective Circuit Fault Simulator 010001010100010101010 … Behavior Signature 010100110000101010100 … 101000100001011101100 … 010100010100011101100 … 000111000101010011110 … Candidate Signatures Diagnosis Algorithm Comparison & Conclusion
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Fault Models Fault Models A fault model is an abstraction of a type of defect behavior A fault instance is the application of a model to a circuit wire, node, gate, etc. Used to create and evaluate test sets For diagnosis, they can be used to simulate and predict faulty behaviors
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Stuck-at Fault Model Stuck-at Fault Model The most-used fault model (by far) Simple to simulate Effective for testing, fault grading, and diagnosis of some defects Many fault scenarios are not well represented by the stuck-at model 0/ 1 0/ 1 1 Node A stuck-at 1: (Fault-free/ faulty logic values) A B
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Shorts are a common defect type in CMOS Different bridging fault models have varying accuracy and precision, from simplistic to very sophisticated Bridging Fault Model Bridging Fault Model 0 1 1 1 0 1/ 0 X Y Nodes X and Y bridged: Node X forces Y to a value of 0
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Statement of Philosophy Statement of Philosophy Defect model isn’t known beforehand : A single-model algorithm will not be robust Fault models are necessary : Fault models provide precision and guidance for physical failure analysis Fault models are unreliable : Expecting defect behavior to correspond exactly with model assumptions and predictions can cause diagnoses to fail Diagnosis is messy : Any data item can be corrupt; don’t make an irreversible decision based on a single piece of information Be practical : Be wary of expensive solutions, and use all available data
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Outline Outline Background & Philosophy Three-Stage Fault Diagnosis IDDQ Fault Diagnosis Small Fault Dictionaries Conclusions and Future Work
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Three-Stage Fault Diagnosis
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