Lab 7 - Laboratory 7 Objective 0.0 The objective of this...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
1 Laboratory 7 0.0 Objective The objective of this laboratory is to design and model a write back cache and memory controller for the KURM data path. Your cache should implement a 64-word store and use a direct mapping method to access elements of the cache. Each cache entry should contain a valid bit, a tag and four 16-bit data values. To access the cache, an address must be split into tag and index values. The index value is used to access an element in the cache array, while the tag value is compared with the tag value stored in the cache entry to determine if the correct value is stored in the cache entry. Because the cache contains words, the low bit of the address can be ignored, as long as memory is being accessed on a word boundary. You should use the cache size to determine how many of the remaining 15 bits are used for the tag and index values. When a memory read is issued to your cache controller, it should determine immediately whether a hit has oc- curred and if the cache value is valid. The tag is used to determine if the memory address is contained in the cache. The valid bit indicates if the stored value is correct. Initially set to 0 , the valid bit will be set when a cache line is loaded from main memory or the CPU. If a hit occurs, cache contents should immediately be returned to the CPU.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

Page1 / 2

Lab 7 - Laboratory 7 Objective 0.0 The objective of this...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online