Unformatted text preview: 1 Laboratory 5 0.0 Objective The objective of this laboratory is to design, build and simulate a pipelined version of your multi-cycle CPU. The instruction set is identical to the single-cycle version. However, now your CPU should have the following stages : You must also design and develop an instruction decoder that transforms OP values into control signals for the pipeline. In implementing this laboratory, you will construct a third architecture for your KURM CPU. In Labo- ratory 4, you implemented an architecture that consisted of a data path entity and a controller entity. In Problem 3, this architecture will be replaced by a new data path entity developed in Problem 1 and a decoder unit in Problem 2. Submit a single VHDL model that integrates the results of Problems 1–3. There is no need to submit separate models for each result. Problem 1 Using your data path from Laboratory 4 as a starting point, implement a five-stage pipelined data path for the KURM processor. Include registers for storing intermediate data between pipeline stages. Your design shouldKURM processor....
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- Fall '08
- Central processing unit, Processor register, CPU cache, Instruction pipeline, data path