Lab 3 - Laboratory 3 Objective 0.0 The objective of this...

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1 Laboratory 3 0.0 Objective The objective of this lab is to develop structural and behavioral models for a register file and an ALU. These com- ponents are basic building blocks for your CPU. The problems must be solved using the components from the KURM RTL library provided with these labs. Problem 1 Using components from the KRM RTL library, develop a behavioral and a structural model of a single input, dual output register file. A block diagram of the register file is shown below. The following entity definition defines the template interface for your register file: entity reg_file is port ( A : in word; -- input data port Aaddr : in nibble; -- register select for input A B,C : out word; -- output data ports Bddr,Caddr : in nibble; -- register select for outputs -- B and C respectively load : in bit; -- synchronous load enable clear : in bit; -- asynchronous, negative logic -- clear signal clk : in bit); -- rising edge triggered clock end entity reg_file; Signals A , B and C represent the single data input and dual data outputs respectively. Aaddr , Baddr ,and Caddr are the register numbers for storing input A data and for outputting B and C data, respectively. When the load signal is asserted, a rising edge on clk causes the data input on A to be stored in the register identified by Aaddr . If the load signal is not asserted, a rising edge has no effect. When the clear signal is asserted, all register values should be set to 0. Note that clear is asynchronous and is negative logic. Implement two architectures for the register file entity. The first architecture should use behavioral techniques
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This note was uploaded on 12/14/2008 for the course CPR E 381 taught by Professor Zambreno during the Fall '08 term at Iowa State.

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Lab 3 - Laboratory 3 Objective 0.0 The objective of this...

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