Lab 2 - Laboratory 2 Objective 0.0 The objective of this...

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1 Laboratory 2 0.0 Objective The objective of this laboratory is to implement an instruction interpreter for the instruction set of the KURM (KU RISC Machine) CPU that will be the result of your project. This device is a simple 9-instruction RISC-style CPU. As in traditional RISC architectures, the instruction set is composed of a small number of fixed-sized instructions with simple addressing modes. All arithmetic and logic operations operate on and store operands within the register file. The only memory addressing mode used by data transfer and branching instructions is register indirect. The word length for this device is 16 bits. Although KURM reads and writes words, memory addresses index bytes. The following table shows the word in memory associated with each address: The low byte of each word is designated as the most significant byte, and the high byte of each word the least significant. Because instructions are 16 bits in length, the program counter must be incremented by 2 to move to the next instruction. There are 16 orthogonal, general-purpose registers available, as well as a 16-bit program counter. Register R 0 contains 0. Instructions specify register IDs using 4-bit values. The program counter cannot be directly addressed, but is affected by branch and jump instructions. Your KURM will implement the following instruction set: All instructions are one word in length, with the format of each instruction shown in the previous table. The high four bits always specify the operation, while the low 12 bits specify registers and offsets, depending on the instruction type. Mathematical operations ( ADD , SUB , AND , OR and SLT ) operate only on registers. Data transfer and branching operations ( LW , SW and BNE ) operate on two registers and an absolute offset value. The jump op- eration ( JMP ) operates on a single 12-bit offset. Mathematical and logical operations treat the low 12 bits as register identifiers. The high four bits represent R d , the middle four R s and the low four R t , as specified in the previous table. Addition, subtraction and set-greater- than treat the contents of R s and R t as 16-bit, 2s-compliment numbers. An overflow value should be generated by these instructions. Conjunction and disjunction treat R s , R t and R d as unsigned, 16-bit values.
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This note was uploaded on 12/14/2008 for the course CPR E 381 taught by Professor Zambreno during the Fall '08 term at Iowa State.

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Lab 2 - Laboratory 2 Objective 0.0 The objective of this...

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