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Unformatted text preview: 1 Laboratory 1 0.0 Objective The objective of this laboratory is to provide you with experience in specifying behavioral and structural VHDL descriptions of familiar components. Problem 1 Develop a behavioral VHDL model for a 4-to-1 word multiplexer (MUX). Your model should work with arbi- trary length words; i.e., you should not place hard constraints on the lengths of inputs and outputs. Develop a test bench for your MUX that demonstrates each function. Problem 2 Develop a behavioral VHDL model for a 1-bit, 2-to-4 demultiplexer. Your device should include an ENABLE sig- nal as well as normal inputs and outputs. Develop a test bench for your VHDL demultiplexer model that demon- strates basic functionality. Simulate your design to demonstrate correctness. Problem 3 Develop a behavioral VHDL model for a 4-bit shift register. Your shift register should implement functions for LOAD, HOLD, RIGHT SHIFT and LEFT SHIFT. In addition to regular inputs, your shift register should provide a SHIFT LEFT INPUT and a SHIFT RIGHT INPUT that input the value shifted into the right-most and left-...
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This note was uploaded on 12/14/2008 for the course CPR E 381 taught by Professor Zambreno during the Fall '08 term at Iowa State.
- Fall '08