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ARM document - The ARM Processor Acorn Risc Machine 1983...

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The ARM Processor
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Acorn Risc Machine 1983 Advanced Risc Machines 1990 Licensed and produced by Apple, IBM, Intel, Motorola, Nintendo, Samsung, Texas Instruments, others Accounts for over 75% of the 32-bit embedded processors
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Evolving architecture: ARM1, ARM2, … ARM6, ARM7, … Variations on basic architecture: StrongArm, Thumb, Xscale, NEON, Jazelle, etc. Resulting in variations in the basic instruction set And, ARM core combined with other components in “custom” CPUs
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Fixed 32-bit instruction length Sixteen 32-bit registers Byte addressable memory Mostly uniform instruction format Typically single cycle operation Conditional execution Instruction set designed to facilitate pipelining
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Figure 3.1. ARM register structure. 31 29 7 0 Program counter R0 R1 31 0 R14 31 0 Status 28 R15 (PC) 30 6 4 CPSR N - Negative Z - Zero C - Carry V- Overflow Condition code flags Processor mode bits register Interrupt disable bits General purpose registers 15
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Figure 3.2. ARM instruction format (Arithmetic, logic, compare, test, and move instructions) Condition 31 OP code 28 27 20 19 16 15 12 11 4 3 0 R n R d Other info R m ARM instructions have fixed 32 bit length, but somewhat varying format depending on instruction type
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Add and Subtract Instructions
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Condition 31 I 28 19 16 15 12 11 0 R n R d 24 0 OP code S Operand 2 0 21 Destination register Operand 1 register Set Condition code flags 0: Do not alter flags 1: Set flags 31 28 19 16 15 12 11 0 R 3 24 0 ADD 0 0 21 Destination register Operand 1 register R 1 R 2 Operand 2 register ADD R3, R1, R2 0 1110 R3 [R1] + [R2] 3 other
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Condition 31 I 28 19 16 15 12 11 0 R n R d 24 0 OP code S Operand 2 0 21 Destination register Operand 1 register Set Condition code flags 0: Do not alter flags 1: Set flags 31 28 19 16 15 12 11 0 R 3 24 0 ADD 0 0 21 Destination register Operand 1 register R 1 R 2 Operand 2 register ADD R3, R1, R2 0 Operand 2 is a register 1110 Do not set the condition codes 3
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Condition 31 I 28 19 16 15 12 11 0 R n R d 24 0 OP code S Operand 2 0 21 Destination register Operand 1 register Set Condition code flags 0: Do not alter flags 1: Set flags ADD R3, R1, R2 11100000100000010011000000000010 31 28 19 16 15 12 11 0 R 3 24 0 ADD 0 0 21 Destination register Operand 1 register 1110 00 0 0100 0 0001 0011 000000000010 R 1 R 2 Operand 2 register ADD R3, R1, R2 0 1110 3
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Condition 31 I 28 19 16 15 12 11 0 R n R d 24 0 OP code S Operand 2 0 21 Destination register Operand 1 register Set Condition code flags 0: Do not alter flags 1: Set flags ADDS R3, R1, R2 11100000100100010011000000000010 31 28 19 16 15 12 11 0 R 3 24 0 ADD 1 0 21 Destination register Operand 1 register 1110 00 0 0100 1 0001 0011 000000000010 R 1 R 2 Operand 2 register ADDS R3, R1, R2 and set condition codes 0 1110 3
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Condition 31 I 28 19 16 15 12 11 0 R n R d 24 0 OP code S Operand 2 0 21 Destination register Operand 1 register Set Condition code flags 0: Do not alter flags 1: Set flags ADD R3, R1, #17 11100100100000010011000000010001 31 28 19 16 15 12 11 0 R 3 24 0 ADD 0 0 21 Destination register Operand 1 register 1110 00 1 0100 0 0001 0011 000000010001 R 1 17 Operand 2 value ADD R3, R1, #17 1 Immediate operand 1110 7
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Condition 31 I 28 19 16 15 12 11 0 R n R d 24 0 OP code S Operand 2 0 21 Destination register Operand 1 register Set Condition code flags 0: Do not alter flags 1: Set flags 31 28 19 16 15 12 11 0 R 3 24 0 SUB 0 0 21 Destination register Operand 1 register R 1 R 2 Operand 2 register SUB R3, R1, R2 0 1110 R3 [R1] - [R2] 3
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ARM document - The ARM Processor Acorn Risc Machine 1983...

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