Chapter1.pdf - Microprocessors and Microcontrollers Ali Pourmohammad [email protected] http\/ele.aut.ac.ir\/~pourmohammad 1 Chapter 1 Z80 Company 4

Chapter1.pdf - Microprocessors and Microcontrollers Ali...

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Microprocessors and Microcontrollers Ali Pourmohammad [email protected] 1
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Company 4 bit 8 bit 16 bit 32 bit 64 bit intel 4004 4040 8008 8080 8085 8088/6 80186 80286 80386 80486 80860 pentium zilog Z80 Z8000 Z8001 Z8002 Motorola 6800 6802 6809 68006 68008 68010 68020 68030 68040 Chapter 1: Z80
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Z80 Pin Assignment 30 31 32 33 34 35 36 37 38 39 40 1 2 3 4 5 14 15 12 8 7 9 10 13 27 19 20 21 22 28 18 23 6 24 16 17 26 25 11 29 M1 - MREQ - IORQ - RD - WR - RFSH - HALT - WAIT - INT - NMI - RESET - BUSRQ - BUSAK - + 5V GND Z - 80 CPU A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 Address Bus Data Bus System Control Lines CPU Control Lines Bus Control Lines Chapter 1: Z80
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Z80 Pin Description A15-A0 : Address bus (output, active high, 3-state). Used for accessing the memory and I/O ports During the refresh cycle the I is put on this bus . D7-D0 : Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts. RD: Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O WR: Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location . Chapter 1: Z80
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Z80 Pin Description MREQ Memory Request (output, active Low, 3-state). Indicates memory read/write operation. IORQ Input/Output Request(output, active Low,3-state) Indicates I/O read/write operation. M1 Machine Cycle One (output, active Low). Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle RFSH Refresh (output, active Low). Together with MREQ indicates refresh cycle. Lower 7-bits address is refresh address to DRAM Chapter 1: Z80
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Z80 Pin Description INT Interrupt Request (input, active Low). Interrupt Request is generated by I/O devices. Checked at the end of the current instruction If flip-flop (IFF) is enabled. NMI Non-Maskable Interrupt (Input, negative edge-triggered). Higher priority than INT. Recognized at the end of the current Instruction Independent of the status of IFF Forces the CPU to restart at location 0066H. Chapter 1: Z80
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Z80 Pin Description BUSREQ Bus Request (input, active Low). higher priority than NMI recognized at the end of the current machine cycle. forces the CPU address bus, data bus, and MREQ , IORQ , RD, and WR to high-imp. BUSACK Bus Acknowledge (output, active,Low) indicates to the requesting device that address, data, and control signals MREQ, IORQ, RD, and WR have entered their high- impedance states. Chapter 1: Z80
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Z80 Pin Description RESET Reset (input, active Low). RESET initializes the CPU as follows: Resets the IFF Clears the PC and registers I and R Sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state And all control output signals go to the inactive state. must be active for a minimum of three full clock cycles before the reset operation is complete.
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