synopsys_test_6301_2016.pdf - The University of Texas at Dallas Dept of Electrical Engineering EEDG\/CE 6301 Advanced Digital Logic EEDG\/CE 6303 Testing

synopsys_test_6301_2016.pdf - The University of Texas at...

This preview shows page 1 - 3 out of 11 pages.

The University of Texas at DallasDept. of Electrical EngineeringEEDG/CE 6301: Advanced Digital LogicEEDG/CE 6303: Testing and Testable Design(Instructor: Mehrdad Nourani)A Quick Tool Setup and Tutorialfor Synthesis & Test Using SYNOPSYS ToolsetDISCLAIMER:The following steps aim at your setting SYNOPSYS toolset and run-ning a sample VHDL program. SYNOPSYS is a large commercial CAD tool suite withmany additional options that are not explained here. What we explain here is the mini-mum to run few tools. Nothing is guaranteed here. With this new version of SYNOPSYSthat we installed, there might be problems in this document and some commands maynot work exactly as explained. Proceed cautiously and use it at your own risk. I en-courage you to assign enough time to familiarize yourself with this tool to be able to useit efficiently. Please report problems, corrections and suggestions about this documentto[email protected].1SetupMost of the CAD tools, including SYNOPSYS, are accessible in various labs with UNIX worksta-tions in EC building including EC 4.308 (VLSI CAD Lab) and EC 4.324 (Solarium Lab). Morespecifically, using workstations in EC 4.324 is recommended due to their faster speed and largerRAM. All CAD tools required for this course, run in Solarium Lab.Due to frequent upgrades,sometimes they may not run in other labs. Many of these tools, including SYNOPSYS, provideshell commands to allow user run them. This means that you can telnet to one of these machinesremotely using ”ssh” and run them.• You need to be familiar with the basic UNIX commands and one UNIX text editor (VI,EMACS, GVIM, EDIT, etc.) . The “QuickUNIXGuide” also posted in the course websitecan be a good start.• In order to run CAD tools in your UTD UNIX account, make sure that your environmentvariables are set correctly: Remember that in UNIX the files whose names start with a “.”(e.g..login) are hidden, to view them type “ls -a”.In a new shell, type in the following command at the prompt in order to enable theenvironment variables:source /home/cad/synopsys2007.12/testprofilePlease note that if you source differently (i.e. the way that you source CAD files for othercourses), you will need to close the console and open a new one to source as explained above.This would allow the environment variables to be taken into effect correctly.1
Background image
• Make a directory in your home directory. For example, SYNOPSYS. Note that “˜” refers toyour root directory.mkdir ˜ /SYNOPSYS• Within this directory you should have a directory called WORK. This directory is sometimesused by Synopsys tools to hold temporary values.mkdir ˜ /SYNOPSYS/WORK2Preparation for Testing2.1Netlist RequirementsIn order to stop tetramax from optimizing the circuit, your RTL description should adhere to thefollowing guidelines:1 The RTL description can be in either Verilog or VHDL.Ensure that the coding style mustbe completely structural in nature.
Background image
Image of page 3

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture

  • Left Quote Icon

    Student Picture