{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

vlogwsf17_lecture3_handout.pdf

vlogwsf17_lecture3_handout.pdf - ECE 508 WKSP Verilog...

Info iconThis preview shows pages 1–5. Sign up to view the full content.

View Full Document Right Arrow Icon
1 ECE 508: WKSP: Verilog Workshop Lecture 3: Verilog Elements (wrap-up) Modules and Ports Gate Level Modeling Roy Kravitz Electrical and Computer Engineering Maseeh College of Engineering and Computer Science ECE 508 WKSP: Verilog Workshop Verilog Elements (wrap-up)
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
2 ECE 508 WKSP: Verilog Workshop Review: Nets Have logic values continuously driven on them by the outputs of devices or assignments Used to connect things together a b y May be vectors (more than one bit) and/or arrays (more than one element) Assigned using assign statement or by module input port Cannot be assigned in a procedural ( always or initial ) block ; Type declaration may be combined with port declaration: input wire en; input wire [7:0] a, b; output wire signed [15:0] op1; wire y; assign y = a & b; net // Implicit Continuous Assignment wire y = a & b; ECE 508 WKSP: Verilog Workshop Review: Reg Variables Represent storage elements But do not necessarily imply a physical (hardware) register! You can do combinatorial logic w/ reg variables Retain their value until another value is assigned to them May only be changed by assigning value to them May be vectors (more than one bit) and/or arrays (more than one element) Must be assigned to in a procedure (initial or always) block or when the variable is declared Examples: reg y = 0; //1-bit storage element reg [7:0] DataByte; //8-bit storage element reg [1:8] Backwardsbus; //MSB is always the left number reg [31:0] Memory [255:0] //array of 256 32-bit elements
Background image of page 2
3 ECE 508 WKSP: Verilog Workshop Other Reg Variable Types integer - Signed variable of fixed width (usually 32 bits) also used for vector and loop indices real - floating point (not synthesizable) time - related to simulation time (not synthesizable) Integer, real and time variables can be arrays real [9:0] //array of ten real numbers ECE 508 WKSP: Verilog Workshop Variable Declaration Summary Net type wire - unsigned variable of any bit size wire signed - signed variable of any bit size Register type reg - unsigned variable of any bit size reg signed - signed variable of any bit size integer - signed variable (≥ 32 bits) Declaration Syntax: <data_type> [m:n] <signal name>; Signed arithmetic is only performed when both of the operands and the result are signed nets or reg variables Examples wire [15:0] m_out, add_out; //two 16-bit unsigned wires reg state; //one bit wide reg signed [63:0] result; //64-bit signed reg [0:7] big_endian; //8-bit unsigned reg [7:0] little_endian; //8-bit unsigned reg [31:2] word_address; //30-bit unsigned MSB LSB m and n are non-negative integers
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon