vlogwsf17_lecture3_handout.pdf

# vlogwsf17_lecture3_handout.pdf - ECE 508 WKSP Verilog...

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1 ECE 508: WKSP: Verilog Workshop Lecture 3: Verilog Elements (wrap-up) Modules and Ports Gate Level Modeling Roy Kravitz Electrical and Computer Engineering Maseeh College of Engineering and Computer Science ECE 508 WKSP: Verilog Workshop Verilog Elements (wrap-up)

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2 ECE 508 WKSP: Verilog Workshop Review: Nets Have logic values continuously driven on them by the outputs of devices or assignments Used to connect things together a b y May be vectors (more than one bit) and/or arrays (more than one element) Assigned using assign statement or by module input port Cannot be assigned in a procedural ( always or initial ) block ; Type declaration may be combined with port declaration: input wire en; input wire [7:0] a, b; output wire signed [15:0] op1; wire y; assign y = a & b; net // Implicit Continuous Assignment wire y = a & b; ECE 508 WKSP: Verilog Workshop Review: Reg Variables Represent storage elements But do not necessarily imply a physical (hardware) register! You can do combinatorial logic w/ reg variables Retain their value until another value is assigned to them May only be changed by assigning value to them May be vectors (more than one bit) and/or arrays (more than one element) Must be assigned to in a procedure (initial or always) block or when the variable is declared Examples: reg y = 0; //1-bit storage element reg [7:0] DataByte; //8-bit storage element reg [1:8] Backwardsbus; //MSB is always the left number reg [31:0] Memory [255:0] //array of 256 32-bit elements