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1ECE 508: WKSP: Verilog WorkshopLecture 3: Verilog Elements (wrap-up)Modules and PortsGate Level ModelingRoy KravitzElectrical and Computer EngineeringMaseeh College of Engineering and Computer ScienceECE 508 WKSP: Verilog WorkshopVerilog Elements (wrap-up)
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2ECE 508 WKSP: Verilog WorkshopReview: NetsHave logic values continuously driven on them by the outputs of devices or assignmentsUsed to connect things togetherabyMay be vectors (more than one bit) and/or arrays (more than one element)Assigned using assignstatement or by module input portCannotbe assigned in a procedural (always orinitial) block;Type declaration may be combined with port declaration:input wireen;input wire[7:0] a, b;output wiresigned [15:0] op1;wire y;assign y = a & b;net// Implicit Continuous Assignmentwire y = a & b;ECE 508 WKSP: Verilog WorkshopReview: Reg VariablesRepresent storage elementsBut do not necessarily imply a physical (hardware) register!You can do combinatorial logic w/ reg variablesRetain their value until another value is assigned to themMay only be changed by assigning value to themMay be vectors (more than one bit) and/or arrays (more than one element)Must be assigned to in a procedure (initial or always) block or when the variable is declaredExamples:reg y = 0; //1-bit storage elementreg [7:0] DataByte; //8-bit storage elementreg [1:8] Backwardsbus; //MSB is always the left numberreg [31:0] Memory [255:0] //array of 256 32-bit elements