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# HomeworkSolutions1.pdf - in and out of intersections...

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Unformatted text preview: in and out of intersections without mishap. For safe operation, only one train at a time can be present on any given track segment. The track layout seen in Figure 8.1 is divided into four track segments. Each track segment has sensors that are used to detect trains at the entry and exit points. In Figure 8.1, there are two ECE 485/585 Trains A and B. As an example, assume Train A always runs on the outer track loop and Train B on the inner track loop. Assume Microprocessor Systems Design for a moment that Train A has just passed Sensor 4 and is near Switch 3 moving Fall 2017 counterclockwise. Let's also assume that Train B is moving counterclockwise and approaching SensorHomework 1 Solutions 2. Since Train B is entering the common track (Track 2), Train A must be stopped when it reaches Sensor 1, and must wait until Train B has passed Sensor 3 (i.e., Train B is out of the common track). At this point, The track layout of a small electric train system is shown in the figure below. Two the track switches should switch for Train A, Train A will be allowed to enter trains run on the tracks. Train A travels counterclockwise on the outer track while Track 2, and Train B will continue moving toward Sensor 2. train B travels counterclockwise on the inner track. The layout is divided into four The controller is a state machine that uses the sensors as inputs. The segments. To avoid collisions, only one train at a time can be present on a given controller’s outputs control the direction of the trains and the position of the track segment. In this case, it means ensuring that only one train is on the shared switches. However, the state machine does not control the speed of the train. This means that the system controller must function correctly independent of track segment, labeled Track 2 below. Each track segment has sensors at the entry the speed of the two trains. and exit points of the segment to indicate a train is about to pass the sensor. Switch 3 Track 1 Track 3 A B Sensor 5 Sensor 1 Sensor 2 Track 4 Sensor 3 Sensor 4 Track 2 Switch 1 Switch 2 For example, assume Train A has passed Sensor 4 and is nearing Switch 3, moving Figure 8.1 Track layout with input sensors and output switches and output tracks. counterclockwise. Train B, also moving counterclockwise is approaching Sensor 2. Since Train B is about to enter the common track segment (Track 2), Train A must be stopped when it reaches Sensor 1 and wait until Train B has passed Sensor 3, indicating it is no longer on the shared portion of the track. At that point, Train A will be allowed to proceed and Switch 2 will ensure Train A proceeds to the segment designated Track 1. The controller is a finite state machine that uses the sensors (S1 through S5) as inputs. The outputs of the controller control the direction of the trains and the position of the switches. Note that the controller does not control the speed of the trains and it must function independently of the speed of the trains. We ensure the clock rate is fast enough relative to the trains’ speeds to halt a train before it proceeds past a sensor. Moreover a train’s length does not exceed the length of a segment of track. Note that the sensors are not asserted for only a single clock. A train’s direction is controlled by two bits: DA1, DA0 for Train A, and DB1, DB0 for train B. When 00 the train is stopped. When 01, the train goes forward (counterclockwise). When 10, the train operates in reverse (clockwise). The value 11 is illegal and should never be used. 8.3 Switch Direction Outputs (SW1, SW2, and SW3) Switch directions are controlled by asserting the SW1, SW2, and SW3 output signals either high (outside connected with inside track) or low (outside tracks connected). That is, anytime all of the switches are set to 1, the tracks are setup such that the outside tracks are connected to the inside tracks. (See Figure 8.3.) If a train moves the wrong direction through an open switch it will derail. Be careful. If a train is at the point labeled "Track 1" in Figure 8.3 and is moving The switch directions are controlled by SW1, SW2, SW3. When asserted, the to the left, it will derail at Switch 3. To keep it from derailing, SW3 would need corresponding switch is moved to connect the outside with the inside track. The to be set to 0. diagram below depicts the switch positions when all three SW1, SW2, and SW3 are Also, note that Tracks 3 and 4 cross at an intersection and care must be taken to asserted. Note that a train going through an “open” switch will derail. avoid a crash at this point. Switch 3 Track 1 Track 3 State Machine Design: The Electric Train Controller 151 Sensor 5 Sensor 1 Sensor 2 Sensor 3 Track 4 Sensor 4 The state machine’s signal inputs and outputs have been summarized in the Track 2 following figure: Switch 1 Switch 2 et h-3=( Sw3) Figure 8.3Res Track direction if all switches are asserted (SW1 = SW2Switc = SW3 1) Se nsor -5 (S5) Se nsor -4 (S4) FPGA Switc h-2 ( Sw2) Switc h-1 ( Sw1) 8.4 Train Sensor Input Signals (S1, S2, S3, S4, and S5) State The five train sensor input signals Machi ne(S1, S2, S3, S4, and S5) go high when a train Se nsor -3 (S3) ecti on A1 ( DA1) sensor location. It should be noted that Dir sensors (S1, S2, S3, S4, and Dir ecti on A2 ( DA0) S5) do not go high for only one clock cycle. In fact, the sensors fire Se nsor -1 (S1) on B1 (DB1) continuously for many clock cycles per passage ofDiraecti train. This means that if LK Dir ecti on B0 (DB0) yourCdesign is testing the same sensor from one state to another, you must wait for the signal to change from high to low. As an example, if you wanted to count how many times that a train passes Sensor 1, you can not just have an "IF S1 GOTO count-one state" followed by "IF S1 GOTO count-two state." You would need to have a state that sees Sensor (S1, S2, S3, S4, S5) = 1 Train Present S1=‘1’, then S1=‘0’, then S1=‘1’ again before you can be sure that it has passed S1 twice. If your state machine hasPresent two concurrent states that look for = 0 Train not S1=’1’, the state machine will pass through both states in two consecutive clock cycles although the train will have passed S1 only once. Another way (SW1, would be SW3) to detect= S1=’1’, thentoS4=’1’, then S1=’1’ if, in fact, the Switches SW2, 0 Connected Outside Track train was traversing the outside loop continuously. Either method will ensure that the train passed S1 twice. = 1 Connected to Inside Track Se nsor (S2)the is -2 near Train Direction (DA1-DA0) and (DB1-DB0) = 00 Stop = 01 Forward (Counterclockwise) = 10 Backward (Clockwise) Figure 8.4 Train Control State Machine I/O Configuration. Draw a state transition diagram for the model train controller described above. Be sure to label all states and transition arcs. 8.5 An Example Controller Design We will now examine a working example of a train controller state machine. For this controller, two trains run counterclockwise at various speeds and avoid collisions. One Train (A) runs on the outer track and the other train (B) runs on the inner track. Only one train at a time is allowed to occupy the common track. Both an ASM chart and a classic state bubble diagram are illustrated in Figures Create a Verilog module to model a finite state machine implemented from the state transition diagram above. Use the FSM Verilog style employed in the T-Bird tail light example. Create a testbench to verify your design. Reset is synchronous. Note: To make this more robust, we should have Reset determine the position of the trains and go to the appropriate state. However, as specified, the sensors don’t provide enough information to determine the location of the trains. Unless a sensor (e.g. S1) remains on until the next one turns on (e.g. S4), we can’t know for certain whether train A is in the upper section of the track or the lower, shared section. We can also detect bad input conditions (e.g. impossible Sensor inputs given last position and direction of train) and raise an error flag. Finally, we can permit more 154 Rapid Prototyping of Digital Systems Chapter 8 complex behavior such as “parking” the outside track train on Track 4. Or, we could permit the trains to travel clockwise as well as counterclockwise. Sw3 T1 A T3 B S5 S1 S2 S3 T4 S4 T2 Sw1 Sw2 ABout: DA0, DB0 ( DA = 1, DB = 1 ) Sw3 Sw3 T1 B T3 T3 S5 S1 S2 S5 S3 T4 S4 S1 S2 T4 A Sw2 T2 Sw1 Ain: DA0, DB0 ( DA = 1, DB = 1 ) Sw3 Sw3 T1 S2 S5 S3 T4 S4 A S1 S2 T4 B T2 Sw2 T2 Sw1 Bstop: DA0 ( DA = 1, DB = 0 ) S4 T3 A Sw1 S3 Sw2 T1 S5 B S4 Bin: DA0, DB0, Sw1, Sw2 ( DA = 1, DB = 1, Sw1, Sw2 ) T3 S1 S3 B T2 Sw1 A T1 Astop: Sw2 DB0, Sw1, Sw2 ( DA = 0. DB = 1, Sw1, Sw2 ) Figure 8.7 Working diagrams of train positions for each state. Table 8.1 Outputs corresponding to states. State ABout Ain Astop Bin Bstop Sw1 Sw2 Sw3 DA(1-0) DB(1-0) 0 0 0 01 01 0 0 0 01 01 1 1 0 00 01 1 1 0 01 01 0 0 0 01 00 0 1 S4 1 0 S3 Figure 8.5 Example Train Controller ASM Chart. S1 = 0 S2 = 0 ABout DA0, DB0 S2 = d S4 = 1 S2 = 0 S4 = 0 S1 = 1 S2 = d Ain S1 = d S3 = 1 Bin S1 = 0 S2 = 1 DA0, DB0, Sw1, Sw2 DA0, DB0 S2 = 1 S4 = 0 S3 = 1 Bstop DA0 S4 = 0 Figure 8.6 S1 = 0 S3 = 0 S4 = 1 S1 = 1 S3 = 0 Astop DB0, Sw1, Sw2 S3 = 0 Example Train Controller State Diagram. 8.5 and 8.6 contain the same information. They are simply different styles of representing a state diagram. The track diagrams in Figure 8.7 show the states visually. In the state names, "in" and "out" refer to the state of track 2, the track that is common to both loops. 154 Rapid Prototyping of Digital Systems Chapter 8 Description of States in Example State Machine Sw3 T1 A T3 B All States All signals that are not "Asserted" are zero and imply a logical result as described. S5 S1 ABout: "Trains A and B Outside" S2 S3 T4 S4 DA0 Asserted: Train A is on the outside track and moving counterclockwise (forward). DB0 Asserted: Train B is on the inner track T2 (not the common track) and also moving forward. Sw1 Sw2 Note that by NOT Asserting DA1, it is automatically zero -- same for DB1. Hence, the outputs are ABout: DA0, DB0 ( DA = 1, DB = 1 ) DA = “01” and DB = “01”. Sw3 Ain: S1 Sw3 T1 A T1 "Train A moves to Common Track" Sensor 1 has fired eitherB first or at the same time as Sensor 2. T3 T3 Either Train A is trying to move towards the common track, or S5 Both trains areS5attempting to move towards the common track. S2 S3 S4 S1 S2 S3 T4 T4 Both trains are allowed to enter here; however, state Bstop will stop B if both have entered. DA0 Asserted: Train A is on the outside track and moving counterclockwise (forward). A B T2 T2 DB0 Asserted: Train B is on the inner track (not the common track) and also moving forward. Sw1 Sw2 Sw1 Sw2 Ain: DA0, DB0 ( DA = 1, DB = 1 ) S4 Bin: DA0, DB0, Sw1, Sw2 ( DA = 1, DB = 1, Sw1, Sw2 ) Bstop: "Train B stopped at S2 waiting for Train A to clear common track" DA0 common track. Sw3Asserted: Train A is moving from the outside track to theSw3 T1 T1 Train B has arrived at Sensor 2 and is stopped and waits until Sensor 4 fires. SW1 and SW2T3are NOT Asserted to allow the outside track to connect to T3 common track. Bin: S1 "Train B has S5reached SensorS32 before Train A reaches Sensor 1" B S2 A S1 S4 S2 S5 T4 Train B is allowed to enter the common track. Train A is approaching Sensor 1. T4 DA0 Asserted: Train A is on the outside track and moving counterclockwise (forward). B A T2 T2 DB0 Asserted: Train B is on the inner track moving towards the common track. Sw1 Sw2 Sw1 Sw2 DB0, Sw1, track. Sw2 DA = 1, DB 1 = 0is ) set to let the inner track connect to Astop: Bstop: DA0 ( Switch SW1 Asserted: the common ( DA = 0. DB = 1, Sw1, Sw2 ) SW2 Asserted: Switch 2 is set to let the inner track connect to the common track. Figure 8.7 Working diagrams of train positions for each state. S3 S4 Astop: "Train A stopped at S1 waiting for Train B to clear the common track" DB0 Asserted: Train B is on the inner track moving towards the common track. Table 8.1 Outputs to states. SW1 and SW2 Asserted: Switches 1 and 2corresponding are set to connect the inner track to the common track. State ABout Ain Astop Bin Bstop Sw1 Sw2 Sw3 DA(1-0) DB(1-0) 0 0 0 01 01 0 0 0 01 01 1 1 0 00 01 1 1 0 01 01 0 0 0 01 00 Do not be concerned that the switches, sensors, and motor control signals permit 8.6 VHDL Based Example Controller Design more complicated behavior than that which is implemented by the current The corresponding VHDL code for the state machine in Figures 8.5 and 8.6 is controller. shown below. A CASE statement based on the current state examines the inputs At each clock edge, the next state becomes the current to select the next state. state. WITH…SELECT statements at the end of the program specify the module TrainController(Reset, Clock, Sensor1, Sensor2, Sensor3, Sensor4, Sensor5, Switch1, Switch2, Switch3, DA, DB); input Reset, Clock, Sensor1, Sensor2, Sensor3, Sensor4, Sensor5; output Switch1, Switch2, Switch3; output [1:0] DA, DB; reg Switch1, Switch2, Switch3; reg [1:0] DA, DB; parameter ABout Ain Bin Astop Bstop = = = = = 5'b00001, 5'b00010, 5'b00100, 5'b01000, 5'b10000; reg [4:0] State, NextState; always @(posedge Clock) begin if (Reset) State <= ABout; else State <= NextState; end always @(State) begin case (State) ABout: begin Switch1 = 0; Switch2 = 0; Switch3 = 0; DA = 2'b01; DB = 2'b01; end Ain: begin Switch1 = 0; Switch2 = 0; Switch3 = 0; DA = 2'b01; DB = 2'b01; end Bin: begin Switch1 = 1; Switch2 = 1; Switch3 = 0; DA = 2'b01; DB = 2'b01; end Astop: begin Switch1 = 1; Switch2 = 1; Switch3 = 0; DA = 2'b00; DB = 2'b01; end Bstop: begin Switch1 = 0; Switch2 = 0; Switch3 = 0; DA = 2'b01; DB = 2'b00; end default: begin \$display("*** Error: illegal state ***"); \$finish(); end endcase end always @(State, Sensor1, Sensor2, Sensor3, Sensor4, Sensor5) begin case (State) ABout: begin if (Sensor1) NextState = Ain; else if (Sensor2) NextState = Bin; else NextState = ABout; end Ain: begin if (Sensor4) NextState = ABout; else if (Sensor2) NextState = Bstop; else NextState = Ain; end Bin: begin if (Sensor3) NextState = ABout; else if (Sensor1) NextState = Astop; else NextState = Bin; end Astop: begin if (Sensor3) NextState = Ain; else NextState = Astop; end Bstop: begin if (Sensor4) NextState = Bin; else NextState = Bstop; end default: begin \$display("*** Error: illegal state ***"); \$finish(); end endcase end endmodule module test; reg s1, s2, s3, s4, s5; reg clk; reg reset; wire sw1, sw2, sw3; wire [1:0] adir, bdir; // sensor inputs // switch outputs TrainController TC (reset, clk, s1, s2, s3, s4, s5, sw1, sw2, sw3, adir, bdir); initial begin clk = 0; forever #10 clk = ~clk; end // Note that this is not a comprehensive test, just an example to demonstrate use of // free running clock, monitor and clock-based stimulus using, in this case, negative // clock edge initial begin reset = 1; repeat (2) @(negedge clk); reset = 0; repeat (10) @(negedge clk); s1 = 1; repeat (5) @(negedge clk); s2 = 1; repeat (5) @(negedge clk); s4 = 1; s1 = 0; repeat (5) @(negedge clk); \$finish(); end initial begin \$display("clk reset s1 s2 s3 s4 s5 sw1 sw2 sw3 adir bdir"); \$monitor(\$time, " %b %b %b %b %b %b %b %b %b %b %2b %2b", clk, reset, s1, s2, s3, s4, s5, sw1, sw2, sw3, adir, end endmodule Grading guidelines 50 points for compiling, running without errors - 10 points for not following directions for filenames (module, testbench, zip file) - 10 points if simulation didn’t terminate properly - 20 points if warning or error messages from compilation or simulation 10 points for design documentation state transition diagram with all states and transitions labeled output state table (showing outputs for each state) if not included in state transition diagram 20 points for testbench - 10 points if not thorough - 5 points if missing tabular output (so don’t have to debug solely by timing diagram) -5 points if not cycle based 20 points for design module code Note that you might think this could be done with fewer states if we don’t worry about where the train granted use of the shared track is (until the other train approaches the switch controlling access to the shared track). In other words, if Train A has been granted use of the shared track and Train B hasn’t yet reached S2, it doesn’t matter whether Train A is still on the shared track or has passed S4. While this won’t crash the trains, it might not be desired behavior. Note that if Train A passes S4 and only later does Train B arrive at S2, then Train B will remain stopped until Train A is again granted access to the shared track. This gives Train A access to the shared track twice before Train B is permitted to use it. The opposite situation could occur if Train B is granted access to the shared track and Train A hasn’t yet reached S1. While neither train would be indefinitely denied access to the shared track (a situation known as “starvation”), it’s no a “fair” solution in that a train is not guaranteed access before the other train has a second opportunity to access the shared track. ...
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