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dcug_7 - vV-2004.06 Design Compiler User Guide 7 Defining...

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/ 7-1 HOME CONTENTS INDEX E-mail your comments about Synopsys documentation to docs@synopsys.com vV-2004.06 Design Compiler User Guide 7 Defining Design Constraints 7 In addition to specifying the design environment, you must set design constraints before compiling the design. There are two categories of design constraints: Design rule constraints Design optimization constraints Design rule constraints are supplied in the technology library you specify. They are referred to as the implicit design rules. These rules are established by the library vendor, and, for the proper functioning of the fabricated circuit, they must not be violated. You can, however, specify stricter design rules if appropriate. The rules you specify are referred to as the explicit design rules. Design optimization constraints define timing and area optimization goals for Design Compiler. These constraints are user-specified. Design Compiler optimizes the synthesis of the design, in
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/ 7-2 HOME CONTENTS INDEX E-mail your comments about Synopsys documentation to docs@synopsys.com vV-2004.06 Design Compiler User Guide accordance with these constraints, but not at the expense of the design rule constraints. That is, Design Compiler attempts never to violate the higher-priority design rules. Note: In this chapter, setting explicit design rules and optimization constraints is discussed without reference to the particular compile strategy you choose. But the compile strategy you choose does influence your constraint settings. This chapter contains the following sections: Setting Design Rule Constraints Setting Optimization Constraints Verifying the Precompiled Design The task of setting timing constraints can be complicated (especially setting the timing exceptions) and includes the following tasks: Defining a Clock Specifying I/O Timing Requirements Specifying Combinational Path Delay Requirements Specifying Timing Exceptions
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/ 7-3 HOME CONTENTS INDEX E-mail your comments about Synopsys documentation to docs@synopsys.com vV-2004.06 Design Compiler User Guide Setting Design Rule Constraints This section discusses the most commonly specified design rule constraints: Transition time Fanout load Capacitance Design Compiler also supports cell degradation and connection class constraints. For information about these constraints, see the Design Compiler Reference Manual: Constraints and Timing . Design Compiler uses attributes assigned to the design’s objects to represent design rule constraints. Table 7-1 provides the attribute name that corresponds to each design rule constraint. Design rule constraints are attributes specified in the technology library and, optionally, specified by you explicitly. Table 7-1 Design Rule Attributes Design rule constraint Attribute name Transition time max_transition Fanout load max_fanout Capacitance max_capacitance min_capacitance Cell degradation cell_degradation Connection class connection_class
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dcug_7 - vV-2004.06 Design Compiler User Guide 7 Defining...

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