Generating HSPICE netlist from synthesized gate-level netlist This tutorial demonstrates how to generate a HSPICE netlist from a synthesized gate-level Verilog netlist. This procedure consists of 2 steps; importing synthesized gate-level Verilog netlist into Cadence tool and extracting HSPICE netlist from the schematic of the imported Verilog netlist. 1. Setup (1)Complete additional CAD tools setup Complete the steps from 6 to 10 of “Setup Instructions” on VLSI CAD Tools fwebsite. http://www-scf.usc.edu/~ee577/(2)Edit cds.lib file Add the following line in your cds.lib file DEFINE OSU_stdcells /auto/home-scf-06/ee577/design_pd k/osu_stdcells/lib/tsmc018/OSU_stdcells_tsmc018 Add the following line if it is not already there INCLUDE $CDK_DIR/cdssetup/cds.lib 2. Verilog import (1)Launch Cadence tool aludra> icfb & (2)Create a new library to import Verilog netlist CIW => File => New => Library Name: type a library name you want Technology File: check “Don’t need a techfile” Click OK
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