Extracting Top Level Verilog Netlist from Cadence Schematic 1.In icfb window (CIW) go to tools and then choose Synopsys Integration. CIW-ÆToolsÆSynopsys Integration In CSI window Browse to your top level design, and click OK. 2.CSI window will pop up. On CSI go to Session then environment and then change run directory…. CSI ÆSession ÆEnvironment ÆChange run directory… On CSI initialization window correct your path where you want your netlist to be extracted and then click OK. 3.On CSI window under session choose set up and CSI… CSI ÆSession ÆSetup ÆCSI… Then in CSI Options change Netlist format to Verilog HDL
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