nc verilog tutorial

nc verilog tutorial - wire S_out C_out reg A_in reg B_in...

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View Full Document Right Arrow Icon .. 1 of 1 9/5/2007 5:45 AM ////////////////////////////////////////////////////////////////////// // dut.v ////////////////////////////////////////////////////////////////////// module adder1bit(A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; reg [1:0] SUM; reg S, Cout; always @ (A or B or Cin) begin SUM[1:0]=A + B + Cin; S = SUM[0]; Cout = SUM[1]; end endmodule ///////////////////////////////////////////////////////////////// // tb.v ///////////////////////////////////////////////////////////////// `timescale 1ns/10ps `include "dut.v" module adder8_tb;
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Unformatted text preview: wire S_out, C_out; reg A_in; reg B_in; reg C_in; adder1bit Adder (A_in,B_in,C_in,S_out,C_out); initial begin A_in=0; B_in=0; C_in=0; #10; A_in=1; B_in=0; C_in=0; #10; A_in=1; B_in=1; C_in=0; #10; A_in=1; B_in=1; C_in=1; end initial begin $shm_open("adder8.shm"); $shm_probe("AC"); end endmodule ////////////////////////////////////////////////////////////////// // tb.f //////////////////////////////////////////////////////////////// //compile all files-v dut.v +ncaccess+rwc tb.v /////////////////////////////////////////////////////////////// Command: ncverilog -f filename.f +gui...
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  • Spring '08
  • Preadditive category, initial begin, reg C_in, reg A_in, reg B_in, end endmodule /////////////////////////////////////////////////////////////////

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