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Unformatted text preview: Netlist These Views: schematic gate_sch verilog Click More Stop Netlisting at Views: symbol verilog Click OK EE577B CAD Tutorial 2001 Fall, Prof. Beerel Created by Jay Moon (firstname.lastname@example.org) Page 2 of 2 - Create a stimulus file. <Verilog-XL>Stimulus->Verilog <Stimulus Options> Mode: Copy Copy From Directory: . ./adder8bit.func (move directory using File Name Form) File Name: testfixture.new Copy To File Name: testfixture.new Click Make Current Test Fixture and Check Verilog Syntax Click OK- Start the simulation and do the same procedures in the handout #7 to check the adder function. The difference between the previous handout and the previous handout is to use schematic for adder1bit instead of functional description. You should be able to mix functional description and schematic to run verilog simulation. Choosing the cellview in netlist can be controlled by putting the desired sequence in Netlist these views form....
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.
- Spring '08