nc verilog brief tutorial

nc verilog brief tutorial - // testbench: tb.v

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Setting up: In your simulation directory (e.g sim) create a directory work (nc-verilog compile directory) sim> mkdir work create cds.lib file as following sim> echo 'define work work' > cds.lib create an empty hdl.var file as following sim> echo '# Hello' > hdl.var Create the design and test bench verilog files in your sim folder (not in work). Cut paste the following sections and create Three files "dut.v", "tb.v" ////////////////////////////////////////////////////////////////////// // design: adder1bit.v ////////////////////////////////////////////////////////////////////// `timescale 1ns/10ps module adder1bit(A, B, Cin, S, Cout); input A, B, Cin; output S, Cout; reg [1:0] SUM; reg S, Cout; always @ (A or B or Cin) begin SUM[1:0]=A + B + Cin; S = SUM[0]; Cout = SUM[1]; end endmodule // adder1bit /////////////////////////////////////////////////////////////////
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Unformatted text preview: // testbench: tb.v ///////////////////////////////////////////////////////////////// `timescale 1ns/10ps module tb; wire S_out, C_out; reg A_in; reg B_in; reg C_in; adder1bit Adder (A_in,B_in,C_in,S_out,C_out); initial begin A_in=0; B_in=0; C_in=0; #10; A_in=1; B_in=0; C_in=0; #10; A_in=1; B_in=1; C_in=0; #10; A_in=1; B_in=1; C_in=1; end endmodule Create your compile and run script note: the first line has to be "#! /usr/bin/csh -f" ----------------------------------------------- #! /usr/bin/csh -f # analyze the design and testbench verilog ncvlog -work work adder1bit.v ncvlog -work work tb.v # elaborate the top level (tb) ncelab -work work -access +rwc work.tb # start and run the simulation with gui ncsim -gui work.tb ----------------------------------------------- Make the script executable sim> chmod u+x run.csh Now compile and run...
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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nc verilog brief tutorial - // testbench: tb.v

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