PrimeTime_Tutorial - A Short Tutorial on PrimeTime EE577B...

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A Short Tutorial on PrimeTime EE577B Instructor: Prof. Rashed Z. Behatti Prepared by: Ehsan Pakbaznia Fall 2007 PrimeTime setup Source CAD tools setup file. %source ~ee577/vlsi_tools.csh Check if PrimeTime is installed on your account %which pt_shell You should get the following: /usr/usc/synopsys/2006.12/sparcOS5/syn/bin/pt_shell Start PrimeTime Make a new directory in your root and call it “sta”: %mkdir sta In the “sta” directory make two new directories named “designs” and “scripts” %mkdir designs scripts NOTE: You will use the “designs” directory to copy all your synthesized verilog files (input files for the PrimeTime) and “scripts” directory to keep all the script files. I have prepared a PrimeTime setup file and a sample tcl script file. Please copy these files into your “sta” directory and “sta/scripts/” drirectory, respectively: %cp ~ee577/tmp/.synopsys_pt.setup ~/sta/. %cp ~ee577/tmp/sta_tut.tcl ~/sta/scripts/. NOTE: sta_tut.tcl is just a sample script file. You have to modify this file in order to make it appropriate for your design. Start the PrimeTime shell at ~/sta/ directory . %pt_shell PrimeTime displays the version number and copyright notice, followed by the pt_shell prompt. Read the Design and Library Files pt_shell> read_verilog ./designs/ ex1_design.v Loading verilog file ' . ../sta/designs/ex1_design.v' 1 1
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The 1 returned by the command indicates successful completion. NOTE: ex1_design.v is your synthesized verilog (output of design compiler) which has to be copied in “ ~/sta/designs/ ” directory. Link the design: Link the design to the library. pt_shell> link_design Loading db file ' . .. /tsmc018/osu018_stdcells.db' Linking design ex1_design . .. Designs used to link ex1_design:
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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PrimeTime_Tutorial - A Short Tutorial on PrimeTime EE577B...

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