Synopsys Synthesis_tutorial

Synopsys Synthesis_tutorial - University of Southern...

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University of Southern California Dr. Rashed Z. Bhatti EE577b Synthesis with Synopsys Design Compiler Design Compiler Setup Source CAD tools setup file. aludra >cd ee577b aludra/ee557b > source ~ee577/vlsi_tools.csh Directory Setup Follow the steps below in your favorite ee577b directory aludra/ee557b > mkdir syn aludra/ee557b/syn > cd syn aludra/ee557b/syn > mkdir db netlist report script sdf sim src aludra/ee557b/syn > cp ~ee577/synthesis/.synopsys_dc.setup . Running Design Compiler - Start Design Compiler aludra/ee557b/syn > dc_shell-t Ignore the error message when Design Compiler is being started. Synthesis Checklist 1. When you read a Verilog source file into Design Compiler, Design Compiler analyzes and elaborates the source code and generates messages. Read the messages carefully and check the following points. a. Check missing inputs in sensitivity list. b. Check messages about “Inferred memory devices”. These messages will be generated when there is a memory device (FFs, latches) in your design. I. Remove unwanted latches . If there are unwanted latches (should be a FF or should be a combinational logic, e.g. missing “else”), modify your source code. II. Remove unwanted FFs . If there are unwanted FFs (should be a combinational logic) modify your source code. III.
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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Synopsys Synthesis_tutorial - University of Southern...

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