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handout7cadence - EE577B CAD Tutorial 2001 Fall Prof Beerel...

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EE577B CAD Tutorial 2001 Fall, Prof. Beerel Created by Jay Moon ([email protected]) Page 1 of 4 EE577B CAD Handout #7 Cadence: Using Verilog-XL Integration (Part 1) History 9/14/2001: Created by Jay Moon Prerequisite None Purpose In this handout, you will get familiar with the Verilog-XL integration user interface for running a simulation. - Copy setup files from ee577 account to your working directory cp ~ee577/ee577bb/setup/.cdsinit . cp ~ee577/ee577bb/setup/.cdsplotinit . cp ~ee577/ee577bb/setup/cds.lib . cp ~ee577/ee577bb/setup/schBindKeys.il . cp ~ee577/ee577bb/setup/display.drf . - Create library “Adder8func” - Create cellview “adder1bit” with view name “functional” (Tool: Verilog-Editor) - Complete adder1bit verilog model as shown below. module adder1bit(Cout, S, A, B, Cin); output Cout, S; input A, B, Cin; reg [1:0] SUM; reg S; reg Cout; wire A, B, Cin; always @(A or B or Cin) begin SUM[1:0] = A + B + Cin; S = SUM[0]; Cout = SUM[1]; end endmodule - Save the file and quit the editor. You see message in the CIW showing you that a syntax check is being done. A “Done” appears in the CIW when the syntax analysis is complete.
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