MCmodels

MCmodels - CY SaritaV. Adve Rice University Kourosh...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
Sarita V. Adve Rice University Kourosh Gharachorloo Digital Equipment Corporation The memory consistency model of a system affects performance, programmability, and portability. This article describes several models in an easy to understand way. Computer CY he shared memory programming model has several advantages over the message passing model. In particular, it simplifies data partitioning and dynamic load distribution. Shared memory sys- tems are therefore gaining wide acceptance for both technical and com- mercial computing. To write correct and efficient shared memory programs, programmers need a precise notion of shared memory semantics. For example, in the program in Figure 1 (a fragment from a program in the Splash applica- tion suite), processor P1 repeatedly updates a data field in a new task record and then inserts the record into a task queue. When no tasks are left, P1 updates a pointer, Head, to point to the first record in the task queue. Meanwhile, the other processors wait for Head to have a non-null value, dequeue the task pointed to by Head in a critical section, and read the data in the dequeued task. To ensure correct execution, a program- mer expects that the data value read should be the same as that written by P1. However, in many commercial shared memory systems, the proces- sors may observe an older value, causing unexpected behavior. The memory consistency model of a shared memory multiprocessor for- mally specifies how the memory system will appear to the programmer. Essentially, a memory consistency model restricts the values that a read can return. Intuitively, a read should return the value of the “last” write to the same memory location. In uniprocessors, “last” is precisely defined by the sequential order specified by the program, called the program order. This is not the case in multiprocessors. For example, in Figure 1 the write and read of Data are not related by program order because they reside on two different processors. The uniprocessor model, however, can be extended to apply to multi- processors in a natural way. The resulting model is called sequential con- sistency. Informally, sequential consistency requires that all memory operations appear to execute one at a time and that all operations of a sin- gle processor appear to execute in the order described by that processor’s program. For Figure 1, this model ensures that the reads of the data field will return the new values written by processor P1. Sequenual consistency provides a simple, intuitive programming model. However, it disallows many uniprocessor hardware and compiler optimizations. For this rea- son, many relaxed consistency models have been proposed, several of which are supported by commercial architectures.
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

Page1 / 11

MCmodels - CY SaritaV. Adve Rice University Kourosh...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online