Adder_Design_Module

Adder_Design_Module - CMOS VLSI Design Adders Textbook by...

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CMOS VLSI Design Adders Textbook by: Neil Weste and David Harris 3rd Edition, Addison-Wesley
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Harris-Adders 2 Outline ± Single-bit Addition ± Carry-Ripple Adder ± Carry-Skip Adder ± Carry-Lookahead Adder ± Carry-Select Adder ± Carry-Increment Adder ± Tree Adder
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Harris-Adders 3 Single-Bit Addition Half Adder Full Adder 0 1 1 1 1 0 0 1 1 0 1 0 0 0 0 0 S C out B A 1 1 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 S C out C B A AB S C out C S C out out SAB C =⊕ =⋅ out (,,) SABC C MAJ ABC =⊕⊕ =
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Harris-Adders 4 PGK ± For a full adder, define what happens to carries – Generate: C out = 1 independent of C – Propagate: C out = C – Kill: C out = 0 independent of C – Note that G A B =⋅ P A B =⊕ KA B .. P AB AB G K =+= +
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Harris-Adders 5 Full Adder Design I ± Brute force implementation from equations out (, , ) S ABC C MAJ A B C =⊕⊕ = A B C S C out MAJ A B C A BB B A C S C C C B AA A B C B A C B B C C out C A A B B
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Harris-Adders 6 Full Adder Design II ± Factor S in terms of C out ± Critical path is usually C to C out in ripple adder S S C out A B C C out MINORITY () out S ABC A B C C =+ + +
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Harris-Adders 7 Layout ± Clever layout circumvents usual line of diffusion – Use wide transistors on critical path – Eliminate output inverters
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Harris-Adders 8 Full Adder Design III ± Complementary Pass Transistor Logic (CPL) – Slightly faster, but more area A C S S B B C C C B B C out C out C C C C B B B B B B B B A A A
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Harris-Adders 9 Full Adder Design IV ± Dual-rail domino – Very fast, but large and power hungry – Used in very fast multipliers C out _h A_h B_h C_h B_h A_h φ C out _l A_l B_l C_l B_l A_l φ S_h S_l A_h B_h B_h B_l A_l C_l C_h C_h φ
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Harris-Adders 10 Carry Propagate Adders (CPA) ± N-bit adder called CPA – Each sum bit depends on all previous carries – How do we compute all these carries quickly? + B N...1 A N...1 S N...1 C in C out 11111 1111 +0000 0000 A 4...1 carries B 4...1 S 4...1 C in C out 00000 1111 +0000 1111 C in C out
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Harris-Adders 11 Carry-Ripple Adder (CRA) ± Simplest design: cascade full adders – Critical path goes from C in to C out – Design full adder to have fast carry delay C in C out B 1 A 1 B 2 A 2 B 3 A 3 B 4 A 4 S 1 S 2 S 3 S 4 C 1 C 2 C 3
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Harris-Adders 12 Inversions ± Critical path passes through majority gate – Built from minority + inverter – Eliminate inverter and use inverting full adder C out C in B 1 A 1 B 2 A 2 B 3 A 3 B 4 A 4 S 1 S 2 S 3 S 4 C 1 C 2 C 3
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Harris-Adders 13 Generate / Propagate ±
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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Adder_Design_Module - CMOS VLSI Design Adders Textbook by...

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