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EE477L_Review_I

EE477L_Review_I - CMOS Digital Integrated Circuits EE477...

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CMOS Digital Integrated Circuits EE477 Review Part I Spring 2007 Dept. of Electrical Engineering – Systems University of Southern California
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M Pedram, USC/EE MOSFET ( M etal O xide S emiconductor F ield E ffect T ransistor ) is a majority carrier device Electrons are the majority carrier for an N-channel FET; holes are the majority carrier for a P-channel FET. By contrast, a BJT (Bipolar Junction Transistor) is a minority carrier device Electrons are the minority carrier in the base region of an NPN transistor Types of MOSFET Devices: N channel enhancement mode: normally OFF; V T > 0 P channel enhancement mode: normally OFF; V T < 0, I ds < 0 MOSFET Transistor Theory
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M Pedram, USC/EE Physical Structure of an N-Channel Enhancement-Type MOSFET
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M Pedram, USC/EE Circuit symbols for n-channel and p-channel enhancement-type MOSFETs. Types of MOSFET Devices
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M Pedram, USC/EE Operating in the linear region Operating at the edge of saturation Operating beyond saturation Cross-sectional View of an nMOS Transistor
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M Pedram, USC/EE For V SB =0, the threshold voltage is denoted as V T0 or V T0n,p 0 0 2 OX B T GC F OX OX Q Q V C C φ = Φ nMOS transistor: 2 | 2 | ln pMOS transistor: 2 | 2 | ln BO A S i F i F A BO D S i F D F i Q qN n kT q N Q qN N kT q n ε φ φ ε φ φ = − = = = Φ GC Ö The work function difference between the gate and the channel Q OX Ö positive charge density at the gate Si-oxide interface due to impurities and lattice imperfections at the interface (Sign is always positive) φ F Ö The substrate Fermi potential Q BO Ö depletion charge density at surface inversion Threshold Voltage of an NMOS Transistor
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M Pedram, USC/EE Threshold voltage determinants: - Gate conductor materials - Gate oxide material & thickness - Substrate doping - Channel Ion Implantation, N I - p-type (n-type) impurities, V T is made more positive (negative) - Impurities in Si-oxide interface, Q ox - Source-bulk voltage, V SB - Temperature, T ( ) ( ) 0.55 heavily doped n-type polysilicon gate (edge of conduction band) 0.55 heavily doped p-type polysilicon gate (edge of valence band) GC F F gate F gate V V φ φ φ Φ = = Threshold Voltage (Cont’d) OX OX OX C t ε = 12 1 12 1 0.34 10 , 1.06 10 ox si Fcm Fcm ε ε = × = ×
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M Pedram, USC/EE For V SB 0, the threshold voltage is denoted as V T or V Tn,p 2 OX B T GC F OX OX Q Q V C C φ = Φ 2 | 2 | B A Si F SB Q qN V ε φ = − + 0 0 0 0 2 B OX B B B B GC F T OX OX OX OX Q Q Q Q Q Q V C C C C φ = Φ = 0 2 where ( | 2 | | 2 |) A Si B B F SB F OX OX qN Q Q V C C ε φ φ = − + 0 ( | 2 | | 2 |) T T F SB F V V V γ φ φ = + + 2 where body effect coefficient A Si OX qN C ε γ = = Threshold Voltage (Cont’d) Reverse body bias V SB Sign=positive
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M Pedram, USC/EE Negative Positive γ Negative Positive V SB * Positive Negative Q B0 , Q B Positive Negative Φ F pMOS nMOS Parameter Signs of Key Parameters * For the typical reverse body biasing condition
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M Pedram, USC/EE NMOS I D -V DS and I D -V GS Curves ( ) 2 0 2 0 .
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