Datapath_Design_Module

Datapath_Design_Module - CMOS VLSI Design Datapath...

Info iconThis preview shows pages 1–7. Sign up to view the full content.

View Full Document Right Arrow Icon
CMOS VLSI Design Datapath Functional Units Lecture Notes by: D. Harris Revised by: M. Pedram Textbook by: Weste and Harris 3rd Edition, Addison-Wesley
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Datapath Modules 2 Outline ± Two's Complement Arithmetic ± Comparators ± Shifters ± Multi-input Adders ± Multipliers
Background image of page 2
Datapath Modules 3 Two's Complement ± The two's complement of a binary number is the value obtained by subtracting the number from a large power of two (specifically, from 2 N for an N-bit two's complement) ± A two's-complement system or two's-complement arithmetic is a system in which negative numbers are represented by the two's complement of the absolute value ± To negate a two's complement number, invert all the bits then add 1 to the result. Bit overflow is ignored, which is the normal case with zero -128 = 0 0 0 0 0 0 0 1 -127 = 1 0 0 0 0 0 0 1 -2 = 0 1 1 1 1 1 1 1 -1 = 1 1 1 1 1 1 1 1 0 = 0 0 0 0 0 0 0 0 1 = 1 0 0 0 0 0 0 0 2 = 0 1 0 0 0 0 0 0 127 = 1 1 1 1 1 1 1 0 sign bit 8-bit two's complement integers
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Datapath Modules 4 Sign Extension ± When turning a two's complement number with a certain number of bits into one with more bits (e.g., when copying from a 1 byte variable to a two byte variable), the sign bit must be repeated in all the extra bits 1111 1101 1101 -3 0000 0101 0101 5 8-bit two's complement 4-bit two's complement Decimal ± Similarly, when a two's complement number is shifted to the right, the sign bit must be maintained. However when shifted to the left, a 0 is shifted in. These rules preserve the common semantics that left shifts multiply the number by two and right shifts divide the number by two sign-bit repetition in 4 and 8-bit integers
Background image of page 4
Datapath Modules 5 Addition ± Adding two's complement numbers requires no special processing if the operands have opposite signs: the sign of the result is determined automatically 11111 111 (carry) 0000 1111 (15) + 1111 1011 (-5) ================ 0000 1010 (10) ± This process depends upon restricting to 8 bits of precision; a carry to the (nonexistent) 9th most significant bit is ignored, resulting in the arithmetically correct result of 10 ± If the last two carry bits (the ones on far left of the top row) are both 1's or both 0's, the result is valid; if the last two carry bits are "1 0" or "0 1", a sign overflow has occurred 0111 (carry) 0111 (7) + 0011 (3) ========== 1010 (-6) invalid!
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Datapath Modules 6 Subtraction ± Like addition, the advantage of using two's complement is the elimination of examining the signs of the operands to determine if addition or subtraction is needed ± Overflow is detected the same way as for addition, by examining the two leftmost (most significant) bits of the borrows; overflow occurred if they are different
Background image of page 6
Image of page 7
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

Page1 / 34

Datapath_Design_Module - CMOS VLSI Design Datapath...

This preview shows document pages 1 - 7. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online