EE477L_Review_II

EE477L_Review_II - CMOS Digital Integrated Circuits EE477L...

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Unformatted text preview: CMOS Digital Integrated Circuits EE477L Review Part II Spring 2007 Dept. of Electrical Engineering Systems University of Southern California M. Pedram USC/EE Cascaded CMOS Inverter Stages = + + + + + = + + + int , , , , i n t , , , , i n t , , : Oxide Capacitances , :Junction Cap. :Interconnect Cap. We typically ignore and terms gd gs gb db sb load gd n gd p db n db p g gd n gd p load db n db p g C C C C C C C C C C C C C C C C C C C C A pulse waveform, V in , is applied to the input of the first stage, analyze the time-domain behavior of V out . M. Pedram USC/EE First-stage CMOS Inverter with a Single Lumped Load , , c D p D n i i i = M. Pedram USC/EE Timing-Related Definitions 50% 1 ( ) 2 OL OH V V V = + 3 2 t t = 1 3 2 PHL PLH t t t t = = Average propagation delay: 2 PHL PLH P + = M. Pedram USC/EE Output Voltage Rise and Fall Times = + = + 10% 90% 0.1 ( ) 0.9 ( ) OL OH OL OL OH OL V V V V V V V V B A t t = D C t t = M. Pedram USC/EE Calculation of Delay Times = = = = 50% , , 50% , , , , . . ( ) . . ( ) : average current during high-to-low output transition : average current during low-to-high out load HL load OH PHL avg HL avg HL load LH load OL PLH avg LH avg LH avg HL avg LH C V C V V I I C V C V V I I I I = = = + = = = = = + = = , 5 % , 50% put transition 1 [ ( , ) ( , )] 2 1 [ ( , ) ( , )] 2 avg HL c in OH out OH c in OH out avg LH c in OL out c in OL out OL I i V V V V i V V V V I i V V V V i V V V V Average Capacitance Current Method: M. Pedram USC/EE Delay Calculation: Differential Equation Method For CMOS, with V OH =V DD and V OL =0, we can write: = + , , , , 2 4 ( ) ln( 1) ( ) ( ) T n DD T n load PHL n D D T n D D T n D D V V V C k V V V V V Furthermore, with V OL =0 and V OH =V DD , we have: = + , , , , 2 4 ( ) ln( 1) ( ) T p DD T p load PLH DD p D D T p D D T p V V V C V k V V V V M. Pedram USC/EE Delay for Non-ideal Step Input We consider the case where input waveform is not ideal (step-input) and it has finite rise and fall times, r and f . Empirical delay corrections are as follows: where PHL (step-input) and PLH (step-input) denote the propagation delays for the ideal step input. = + = + 2 2 2 2 ( ) ( ) ( ) 2 ( ) ( ) ( ) 2 r PHL PHL f PLH PLH actual step input actual step input M. Pedram USC/EE Load Calculation for a CMOS Inverter Driving FO3 + + + = + = + + = + + , , i n t , , , , , , , , , , 3 where ( ) 2( ) ( ) 2( ) ( ) load g db n db p g n p o x db n n drain j n eq n n drain jsw n eq n db p p drain j p eq p p drain jsw p eq p C C C C C C W W L C C W D C K W D C K s w C W D C K W D C K s w M. Pedram USC/EE Interconnect Capacitance Estimation Interconnect running above substrate Influence of fringing electric fields upon the parasitic wire capacitance. M. Pedram USC/EE Interconnect Capacitance Estimation...
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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EE477L_Review_II - CMOS Digital Integrated Circuits EE477L...

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