Dynamic_Power_Minimization_Module

Dynamic_Power_Minimization_Module - CMOS Digital Integrated...

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CMOS Digital Integrated Circuits Dynamic Power Minimization y Spring 2007 Dept. of Electrical Engineering – Systems niversity of Southern California University of Southern California
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troduction Introduction • Power consumption and heat removal are limited by practical considerations: – Low power applications must be battery powered any must be light weight power < few watts – Many must be light weight power < ~few watts – Disposable batteries can cost >> $500/watt over life of device – Rechargeables can cost > $50/watt over life of device. • Home electronics is limited to <~1000W by heating of the room and cost of electricity. igh performance is limited by difficulty of heat removal High performance is limited by difficulty of heat removal from chip (~100 W/chip). (Cost of electricity is ~$5/watt over life.) M. Pedram USC/EE
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verview of Power Consumption Overview of Power Consumption • The power consumption in CMOS digital circuits has three main components: - Capacitive (switching) power consumption ynamic power consumption - Short-circuit (rush-thru) power consumption - Leakage power consumption. } dynamic power consumption • Chips with circuits other than conventional CMOS gates that have continuous current paths between the power supply and e ground, have an extra power component: the ground, have an extra power component: - Static (DC) power consumption. M. Pedram USC/EE
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witching Power Consumption Switching Power Consumption • In digital CMOS circuits, switching power is dissipated when energy is drawn from the power supply to charge up the output node capacitance. • Total capacitive load at the output of a NOR gate consists of i) the output node cap. of the gate itself ii) the total interconnect cap. i) the input cap of the driven gates iii) the input cap. of the driven gates M. Pedram USC/EE A NOR gate driving two NAND gates through interconnection lines
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witching Power Consumption (Cont’d) • Any CMOS logic gate making an output voltage transition can Switching Power Consumption (Cont d) be represented by its nMOS and pMOS networks, and the total load capacitance connected to its output node. M. Pedram USC/EE
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witching Power Consumption (Cont’d) Switching Power Consumption (Cont d) • The average power dissipation can be calculated from the /2 TT tt V dV ⎡⎤ ⎛⎞ energy required to charge up the output node to V DD and charge down the total output load capacitance to ground level. 0/ 2 1 () out out avg out load DD out load T dV PV C d t VVC d t Td t d t =− + ⎢⎥ ⎜⎟ ⎝⎠ ⎣⎦ ∫∫ 2 1 avg load DD PC V = or 2 avg load DD CLK V f = T • The average switching power dissipation of a CMOS gate is independent of transistor characteristics and sizes as long as a where β (activity factor) is the expected number of power- 2 1 2 avg load DD CLK V f β = ⋅⋅⋅ full voltage swing isachieved: M. Pedram USC/EE consuming voltage transitions (0 1 or 1 0) experienced per clock cycle.
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witching Power Consumption (Cont’d) • In complex CMOS logic gates, most of internal circuit nodes
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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Dynamic_Power_Minimization_Module - CMOS Digital Integrated...

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