EE477L_Review_III

EE477L_Review_III - CMOS Digital Integrated Circuits EE477L...

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CMOS Digital Integrated Circuits EE477L Review – Part III Spring 2007 Dept. of Electrical Engineering – Systems University of Southern California
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M. Pedram USC/EE Sequential MOS Logic Circuits • Output levels of a combinational logic circuit at any time are directly determined as Boolean functions of the applied input variables. – Combinational logic circuits do not have the capability of storing any previous event or displaying an output behavior which is dependent upon the previously applied inputs. – Circuits of this type are also called non-regenerative circuits, since there is no feed back relationship between output and input. • The other major class of logic circuits is called sequential circuits, in which the output is determined by the present inputs as well as previously applied inputs.
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M. Pedram USC/EE Types of Sequential Circuits • There are three types for sequential circuits: – Bistable – Monostable – Astable
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M. Pedram USC/EE Behavior of Bistable Elements
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M. Pedram USC/EE SR Latch Circuit • The simple two-inverter circuit has no provision for allowing its states to be changed externally. – The following figure shows the circuit structure of a simple CMOS SR latch which has two triggering inputs, S (set) and R (reset). – The circuit consists of two CMOS NOR2 gates.
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M. Pedram USC/EE SR Latch’s Truth Table • The operation of the CMOS SR latch circuit can be examined in more detail by considering the operation modes of the four nMOS transistors, M1-M4. Truth table of the NOR-based SR latch circuit SR Q n+1 Q n+1 Operation 00 Q n Q n hold 1 010 s e t 0 101 r e s e t 1 100 n o t a l l o w e d Q n+1 Q n+1 Operation V OH V OL V OH V OL M1 and M2 on, M3 and M4 off V OL V OH V OL V OH M1 and M2 off, M3 and M4 on V OL V OL V OH V OL M1 and M4 off, M2 on, or V OL V OL V OL V OH M1 and M4 off, M3 on Operation modes of the transistors in the NOR-based CMOS SR latch circuit
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M. Pedram USC/EE NAND-Based SR Latch
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M. Pedram USC/EE Clocked Latch and Flip-Flop Circuits Clocked SR Latch • All the SR latches we considered so far are asynchronous. • The latch response can be controlled by adding a gating clock signal to the circuit. – This means that the outputs respond to the input levels only during the active period of the clock pulse. – The clock pulse is assumed to be a periodic square waveform, which is simultaneously applied to all clock logic gates in the system.
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M. Pedram USC/EE Clocked NOR-based SR Latch If CK=“0” then inputs have no influence on the outputs, because outputs of the AND gates remain “0”, which forces SR latch to hold its current state. If CK=“1” then input control signals, S and R, are permitted to reach SR latch, and possibly change its state (note that this is an active high implementation.) As in non-clocked SR latch, the input combination S=R=“1” is not allowed.
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M. Pedram USC/EE Operation of Clocked NOR-Based SR Latch • Clearly, the circuit is level sensitive, i.e., when CK=“1” any changes in S and R will be reflected onto outputs.
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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EE477L_Review_III - CMOS Digital Integrated Circuits EE477L...

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