EE477L_Review_IV

EE477L_Review_IV - CMOS Digital Integrated Circuits EE477L...

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CMOS Digital Integrated Circuits EE477L Review – Part IV Spring 2007 Dept. of Electrical Engineering – Systems University of Southern California
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M. Pedram USC/EE Overview of Semiconductor memory types
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M. Pedram USC/EE Equivalent Circuits of Memory Cells SRAM DRAM MASK (Fuse) ROM EPROM (EEPROM)
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M. Pedram USC/EE Typical Random-Access Memory Array Organization
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M. Pedram USC/EE One-Transistor DRAM Cell • Typical 1-T DRAM cell with its access lines – This cell has one word line and only one bit line.
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M. Pedram USC/EE Architecture of 1-T DRAM Cell Array • An array with control circuit, where half-V DD sensing, folded bit line, and shared sense amplifier architectures are incorporated. M0 Sense nodes SA and SAB serve as V DD and Gnd terminals for the pair of cross-coupled inverters in the Bit Line Sense Amplifier. The latch amplifier is shared among 64 BL/BLB pairs.
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M. Pedram USC/EE Timing Diagram for DRAM Read “1” Operation Δ V Δ= + 2 S DD BL C V CC * The cell voltage changes from V DD to V DD /2+ Δ V, i.e., the read operation is destructive . * The levels of BL and BLB eventually reach V DD and ground, respectively. This is called the restoring operation of the cell data.
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M. Pedram USC/EE Timing Diagram of Write “0” Operation Data_IO Data_IOB BL_IO BL_IOB * DRAM cell write time is typically longer than the read time.
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M. Pedram USC/EE Leakage Currents in DRAM Cells Cross-sectional view I leakage =I sub + I tunneling + I j + I cell-to-cell Schematic view
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M. Pedram USC/EE DRAM Input Circuits Inverter type Latch type Diff. amplifier type • Memory input buffers TTL Signal Levels: 0.8V Ù 2.0V
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M. Pedram USC/EE DRAM Output Circuits • Memory output buffers (a) pMOS pull-up and nMOS pull- down structure (b) nMOS pull-up and nMOS pull- down structure TTL level When POE is low, the output buffer is in a tri-state.
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M. Pedram USC/EE Realizations of the 1-T DRAM Cell • DRAM cell with a stacked capacitor • DRAM cell with a trench capacitor
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M. Pedram USC/EE A Detailed View of the Trench Cell Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate
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M. Pedram USC/EE Voltage Sense Amplifiers (a) Differential-output current- mirror type (b) Semi-latch (pMOS latch) type (c) Full cMOS latch type (used in high-speed, low power apps)
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M. Pedram USC/EE Static Read-Write Memory (SRAM)
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M. Pedram USC/EE DRAM Scaling Challenges • Long retention time Æ low OFF current (~1 fA) – Large V T is required • Fast access time Æ high ON current (~100 μ A) – Large ( V GS - V T ) is required
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M. Pedram USC/EE Full CMOS SRAM Cell • Very low standby power consumption, large noise margin, low supply voltage • Basic requirements for setting the (W/L) ratios: – Data-write operation is capable of modifying stored data in SRAM cell.
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EE477L_Review_IV - CMOS Digital Integrated Circuits EE477L...

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