EE477L_Review_V

# EE477L_Review_V - CMOS Digital Integrated Circuits EE477L...

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CMOS Digital Integrated Circuits EE477L Review – Part V Spring 2007 Dept. of Electrical Engineering – Systems University of Southern California

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M. Pedram USC/EE Logical Effort Chip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? Logical effort is a method to make these decisions Uses a simple model of delay Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries ? ? ?
M. Pedram USC/EE Delay in a Logic Gate Express delays in a process-independent unit Delay has two components: Effort delay f = gh (a.k.a. the stage effort) Again has two components abs d d τ = d f p = + τ = 3RC 12 ps in 180 nm process 40 ps in 0.6 mm process

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M. Pedram USC/EE Delay in a Logic Gate (Cont’d) g : logical effort Measures relative ability of a gate to deliver current g 1 for inverter h : electrical effort = C out / C in Ratio of the output to input capacitance p: parasitic delay Represents delay of a gate driving no load Set by the internal parasitic capacitances
M. Pedram USC/EE Delay Plots d = gh + p Electrical Effort: h = C out / C in Normalized Delay:d Inverter 2-input NAND g = 1 p = 1 d = h + 1 g = 4/3 p = 2 d = (4/3)h + 2 Effort Delay: f Parasitic Delay: p 0 1 2 3 4 5 0 1 2 3 4 5 6

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M. Pedram USC/EE Computing Logical Effort Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. Calculate from delay vs. fanout plots or Estimate from transistor width considerations A Y A B Y A B Y 1 2 1 1 2 2 2 2 4 4 C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3
M. Pedram USC/EE Logical Effort of Common Logic Gates 8, 16, 16, 8 6, 12, 6 4, 4 XOR, XNOR 2 2 2 2 2 Tristate / mux (2n+1)/3 9/3 7/3 5/3 NOR (n+2)/3 6/3 5/3 4/3 NAND 1 Inverter n 4 3 2 1 Number of inputs Gate type

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M. Pedram USC/EE Parasitic Delay of Common Logic Gates 2n 8 6 4 XOR, XNOR 2n 8 6 4 2 Tristate / mux n 4 3 2 NOR n 4 3 2 NAND 1 Inverter n 4 3 2 1 Number of inputs Gate type Parasitic delay given in multiples of p inv ( 1)
M. Pedram USC/EE Example: Ring Oscillator Estimate the frequency of an N-stage ring oscillator Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Delay: p = 1 Stage Delay: d = 2 Frequency: f osc = 1/(2*N*d) = 1/4N 31 stage ring oscillator in 0.6 mm process has frequency of ~ 200 MHz

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M. Pedram USC/EE Example: FO4 Inverter Estimate the delay of a fanout-of-4 (FO4) inverter Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Delay: p = 1 Stage Delay: d = 5 d The FO4 delay is about 200 ps in 0.6 mm process 60 ps in a 180 nm process f/3 ns in an f mm process
M. Pedram USC/EE Multistage Logic Networks Logical effort generalizes to multistage networks: Path Logical Effort: Path Electrical Effort: Path Effort: i i G g = out-path in-path C H C = i i i i i F f g h = = 10 x y z 20 g 1 = 1 h 1 = x/10 g 2 = 5/3 h 2 = y/x g 3 = 4/3 h 3 = z/y g 4 = 1 h 4 = 20/z

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M. Pedram USC/EE
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