finalexam_fall05_solutionset

finalexam_fall05_solutionset - EE477 Final Instructor M...

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1 EE477 Final Instructor: M. Pedram Fall 2005 Dec 8, 2005 Exam Duration: 110 minutes Closed book except for one sheet of 8.5” by 11” paper (writings/drawings allowed on one side of the sheet only) Name: SOLUTION SET Student ID #: ________________________________ Problem 1: 50 / 50 Problem 2: 10 / 10 Problem 3: 15 / 15 __________________ Total: 75 / 75
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2 Problem 1 (75 minutes, 50 points) Do all parts. (a) (5 pts.) Consider a 3-input static NOR-Gate. The input signal probabilities are given as: p(a) = 1/4; p(b) = 1/3; p(c) = 1/2. What is the expected dynamic power dissipation at the output of this gate if it is driving a 100fF load at 1GHz with V DD = 1.5V. (2 points) !( ); ! 1313213 () 443432 4 f abcg f abcaa ba b c pg =+ + == + + = ++ = +×+×× = (2 points) 3 1 3 ()( 1 () ) 4 41 6 α= × = × = (1 point) 22 3 100 (1.5) 1 42.2 16 dd clk P CV f f G W =α× × × = × × × = μ (b) (5 pts.) The following figure shows a system containing two edge-triggered flops and some combinational logic connecting the two flops. The flops have the following characteristics: a) Setup time: 0.5ns b) Clock-to-Q delay: 0.8ns c) Hold time: 0.4ns Assuming no clock skew, what is the maximum clock frequency you can run this circuit at? (2 points) min max 2 clk clk Q comb setup T tt t + (2 points) min 0.8 max(8,11) 0.5 12.3 clk T ns += (1 point) max 1 81.3 12.3 clk fM H z n
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3 (c) (5 pts.) Consider the logic function f = ![(a+b)(c+d)e] (where !x is the complement of x .) Draw the schematic and show the stick diagram of a layout using a horizontal ndiff strip parallel to a horizontal pdiff strip. Choose the best ordering of NMOS and PMOS transistors for compact layout. Label each poly line using the input signals (a,b,c,d,e). (2 points) (3 points) The drawing on the right is not a sticks diagram; I have drawn it this way to improve readability. The catch was to put e in between ab and cd pairs. Other orderings, e.g., ecabd results in contiguous n-diffusion, but a break in the p-diffusion. You will receive full credit for solutions like that as well. (d) (5 pts.) What are the voltage levels for logic 0 and logic 1 at nodes X, Y and Z in the circuit below in steady state, assuming that input A goes from V dd to 0 whereas inputs B through E go from 0 to V dd ? The threshold voltage of NMOS transistors is V T . Ignore the body bias effect.
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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finalexam_fall05_solutionset - EE477 Final Instructor M...

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