R_2R_Ladder_DAC

R_2R_Ladder_DAC - 1148 IEEE JOURNAL OF SOLID-STATE...

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Unformatted text preview: 1148 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 8, AUGUST 1998 Design and Implementation of an Untrimmed MOSFET-Only 10-Bit A/D Converter with 79-dB THD Clemens M. Hammerschmied, Student Member, IEEE , and Qiuting Huang, Senior Member, IEEE Abstract A MOSFET-only 10-bit A/D converter is described which achieves a total harmonic distortion of up to 79 dB without trimming or calibration. The maximum conversion rate is 200 ksample/s. Implemented in a 1- " m single-poly technology, it occupies 5.12 mm P and consumes 12 mW from a single 5- V supply. The MOSFET-only R-2R ladder, which is the center of the successive approximation architecture, is analyzed, and design considerations, especially the device dimensions, are given. Measurements of the linear behavior of pure MOSFET ladders are presented. The offset sensitivity of the ladder is examined, and an alternative way of summing the ladder current is suggested. A fast and effective differential current comparator is described. Index Terms A/D converter, comparator, D/A converter, matching, successive approximation. I. INTRODUCTION T HE most important goals in A/D converter design are conversion speed, resolution, and linearity. Linearity, especially, is the focus in the development of high-resolution A/D converters. Besides the high-resolution converters for audio applica- tions, there is a strong need for A/D converters in the medium resolution range (1214 bits) for communications, wireless, or otherwise [1]. Todays implementations often rely on the matching of active or passive components and are usually limited to 10-bit linearity [2], [3], although higher linearity has been reported [4]. An improvement in linearity can be accomplished by using special techniques such as laser or fuse trimming in pro- duction. But this additional manufacturing step is expensive. Another solution is to include selfcalibration circuits on the chip that perform the trimming during power-up or in fixed time intervals. A special case of this technique is digital error calibration sometimes used in high-speed pipelined A/D converters [5][7]. The disadvantages of these techniques, however, are the additional area and power needed for the calibration or correction logic, which can be substantial. It is desirable to have a solution without trimming or calibration, which nevertheless achieves an accuracy of 1214 bits. For that level of linearity, not only must the matching be very good, but also the circuit and layout designs have to comply with the accuracy. An early design decision is Manuscript received October 31, 1997; revised February 26, 1998. The authors are with the Integrated Systems Laboratory, ETH Zentrum, CH-8092 Zurich, Switzerland....
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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R_2R_Ladder_DAC - 1148 IEEE JOURNAL OF SOLID-STATE...

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