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Leakage_Power_Minimization_Module

Leakage_Power_Minimization_Module - Leakage Power...

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Leakage Power Minimization CMOS Digital Integrated Circuits Spring 2007 Dept. of Electrical Engineering – Systems University of Southern California
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Outline Introduction Leakage Currents in CMOS Circuits MTCMOS Technology Design Challenges in MTCMOS Circuits Charge Recycling MTCMOS Optimal Sleep Transistor Distribution in Row Based Optimal Sleep Transistor Distribution in Row Based Layouts Conclusions
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Leakage Components in Bulk CMOS Gate n + n + Source Drain I I Sub P-Substrate Well Gate I RB I RB I Sub Subthreshold current due to the weak inversion conduction (V Gate < V th ) Accounts for 20 40% of total power sub 100 nm technologies I Gate Gate oxide tunneling current was negligible (t ox > 2nm) , increasing due to very thin gate oxides l Di d bi t RB Diode reverse bias current due to high doping concentrations around source/drain
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Leakage v. Active Power Trend P gate P = g 0 fCV 2 + g 1 V 3 + g 2 V 5 g 0 : Switching Constant g 1 : Sub-threshold Leakage Current Constant g 2 : Gate Leakage Current Constant Leakage power is Rising exponentially with technology scaling (e g lower V t ) Rising exponentially with technology scaling (e.g. lower V th , t ox ) Gate leakage control requires high k dielectric under the gate terminal
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Leakage Power Minimization h Techniques Lowering and/or turning off V DD G t l th bi i (V ll ff ff t) Gate length biasing (V th roll off effect) Transistor stacking Applying minimum leakage input vector in sleep mode Body biasing Bias the body of NMOS (PMOS) device V b < GND (V b > V DD ) in sleep mode Utilizing the Multi Threshold CMOS (MTCMOS) technology (possibly combined with V th roll off effect) roll off effect) Static approach: assigns low V th to timing critical logic cells, high V th to other cells Dynamic approach (a k a power gating): requires a control signal Dynamic approach (a.k.a. power gating): requires a control signal (SLEEP signal) to turn off devices in the standby mode
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Gate Length Biasing Slightly increase (bias) the t l th (li idth) f Normalized Delay & Leakage with Gate-Length gate length (linewidth) of devices
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