Leakage_Power_Minimization_Module

Leakage_Power_Minimization_Module - Leakage Power...

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Leakage Power Minimization CMOS Digital Integrated Circuits Spring 2007 Dept. of Electrical Engineering–Systems niversity of Southern California University of Southern California
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utline Outline Introduction Leakage Currents in CMOS Circuits MTCMOS Technology Design Challenges in MTCMOS Circuits Charge Recycling MTCMOS ptimal Sleep Transistor Distribution in Row ased Optimal Sleep Transistor Distribution in Row Based Layouts onclusions Conclusions
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akage Components in Bulk CMOS Leakage Components in Bulk CMOS ate n + n + Gate Source Drain I Sub P-Substrate Well I Gate I RB I RB I Sub Subthreshold current due to the weak inversion conduction (V Gate < V th ) ccounts for 20 0% of total power sub 00 nm technologies Accounts for 20 40% of total power sub 100 nm technologies I Gate Gate oxide tunneling current was negligible (t ox > 2nm) , increasing due to very thin gate oxides l RB Diode reverse bias current due to high doping concentrations around source/drain
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akage v. Active Power Trend Leakage v. Active Power Trend P gate P = g 0 fCV 2 + g 1 V 3 + g 2 V 5 g 0 : Switching Constant g 1 : Sub-threshold Leakage Current Constant g 2 : Gate Leakage Current Constant Leakage power is ising exponentially with technology scaling (e g lower Rising exponentially with technology scaling (e.g. lower V th , t ox ) Gate leakage control requires high k dielectric under the gate terminal
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Leakage Power Minimization Techniques Lowering and/or turning off V DD Gate length biasing (V th roll off effect) Transistor stacking pplying minimum leakage input vector in sleep mode Applying minimum leakage input vector in sleep mode Body biasing Bias the body of NMOS (PMOS) device V b < GND (V b > V DD ) in sleep mode Utilizing the Multi Threshold CMOS (MTCMOS) technology ossibly combined with ll ff effect) (possibly combined with V th roll off effect) Static approach: assigns low V th to timing critical logic cells, high V th to other cells ynamic approach (a k a power gating): requires a control signal Dynamic approach (a.k.a. power gating): requires a control signal (SLEEP signal) to turn off devices in the standby mode
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ate Length Biasing Gate Length Biasing Slightly increase (bias) the
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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Leakage_Power_Minimization_Module - Leakage Power...

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