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midterm_fall05_solutionset

midterm_fall05_solutionset - EE477 Midterm Instructor M...

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1/9 EE477 Midterm Instructor: M. Pedram Fall 2005 Oct 18, 2005 Exam Duration: 90 minutes Closed book except for one sheet of 8.5” by 11” paper (writings/drawings allowed on one side of the sheet only) Name: M. Pedram Student ID #: SOLUTION SET Problem 1: 25 / 25 Problem 2: 10 / 10 Problem 3: 10 / 10 Problem 4: 10 / 10 Problem 5: 15 / 15 Total: 70 / 70
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2/9 NOTE THAT PARTIAL CREDIT INFORMATION WILL BE USED ONLY IF YOUR FINAL ANSWER IS NOT CORRECT. MORE PRECISELY, YOU WILL GET FULL CREDIT FOR A PROBLEM IF YOU HAVE THE CORRECT FINAL ANSWER REGARDLESS OF WHETHER OR NOT YOU HAVE SHOWN THE INTERVENING STEPS. Useful constants ( ε 0, q, ni, etc) are found below. k = 1.38 * 10 -23 J/K q = 1.6 * 10 -19 C ε 0 = 8.85 * 10 -14 F/cm ε Si = 11.7 * ε 0 ε SiO2 = 3.97 * ε 0 n i = 1.45 * 10 10 cm -3 T = 300 K 1- (25 points) Answer any five of the following six questions: 1.a to 1.f. If you answer all of the questions, then we will only grade the first five. (a) (5 points) First, define the VLSI chip manufacturing yield, including functional and parametric yields. Next, enumerate four causes which are typically responsible for VLSI chip reliability problems. Solution: (3 points) Yield can be calculated as the number of good tested chips divided by the total number of tested chips (or more strictly, the total number of chip sites available at the start of the wafer processing.) Functional yield is obtained by testing the functionality of the chip at a speed usually lower than the required chip speed. It captures shorts/opens, stuck-at faults, logic and circuit design faults. Parametric yield captures the effect of uncontrollable process variations as well as dynamic changes in the power/ground network or substrate temperature on the IC performance. It is performed at the required speed of the chips. (2 points) The long-term reliability of a VLSI chip is adversely impacted by: electromigraion, hot-carrier induced aging, oxide breakdown, latch-up in CMOS I/O and internal circuits, single event upset, etc. The short term reliability (i.e., integrity) of an IC is impacted by the power/ground bounce, capacitive crosstalk, non-uniform substrate temperatures, etc. (b) (5 points) Define the inverse subthreshold slope, S, and quantify how it impacts the subthreshold conduction current, e.g., if we reduce the threshold voltage of the nMOS transistor by 2 * S volts, then what would be the change in the I OFF of an inverter when its output is low? In comparison, explain what will happen to I OFF of the inverter if we reduce width of the nMOS transistor by a factor of 2? Solution: (2 points) The inverse subthreshold slope, S, is equal to the voltage required to increase subthreshold conduction current, I D,sub , by 10X, i.e., 2.3 nkT S q = × . (1 point) Recall that , 10 GS T V V S D sub I W × .
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