LECTURE 4 DC AND TRANSIENT RESPONSE

LECTURE 4 DC AND TRANSIENT RESPONSE - Introduction to CMOS...

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Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 2004
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4: DC and Transient Response Slide 2 CMOS VLSI Design Outline q DC Response q Logic Levels and Noise Margins q Transient Response q Delay Estimation
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4: DC and Transient Response Slide 3 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
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4: DC and Transient Response Slide 4 CMOS VLSI Design Activity 1) If the width of a transistor increases, the current will increase decrease not change 2) If the length of a transistor increases, the current will increase decrease not change 3) If the supply voltage of a chip increases, the maximum transistor current will increase decrease not change 4) If the width of a transistor increases, its gate capacitance will increase decrease not change 5) If the length of a transistor increases, its gate capacitance will increase decrease not change 6) If the supply voltage of a chip increases, the gate capacitance of each transistor will increase decrease not change
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4: DC and Transient Response Slide 5 CMOS VLSI Design DC Response q DC Response: V out vs. V in for a gate q Ex: Inverter – When V in = 0 -> V out = V DD – When V in = V DD -> V out = 0 – In between, V out depends on transistor size and current – By KCL, must settle such that I dsn = |I dsp | – We could solve equations – But graphical solution gives more insight I dsn I dsp V out V DD V in
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4: DC and Transient Response Slide 6 CMOS VLSI Design Transistor Operation q Current depends on region of transistor behavior q For what V in and V out are nMOS and pMOS in – Cutoff? – Linear? – Saturation?
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4: DC and Transient Response Slide 7 CMOS VLSI Design nMOS Operation V gsn > V dsn > V gsn > V dsn < V gsn < Saturated Linear Cutoff I dsn I dsp V out V DD V in
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4: DC and Transient Response Slide 8 CMOS VLSI Design nMOS Operation V gsn > V tn V dsn > V gsn – V tn V gsn > V V dsn < V gsn – V tn V gsn < V Saturated Linear Cutoff I dsn I dsp V out V DD V in
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4: DC and Transient Response Slide 9 CMOS VLSI Design nMOS Operation V gsn > V tn V dsn > V gsn – V tn V gsn > V V dsn < V gsn – V tn V gsn < V Saturated Linear Cutoff I dsn I dsp V out V DD V in V gsn = V in V dsn = V out
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4: DC and Transient Response Slide 10 CMOS VLSI Design nMOS Operation V gsn > V tn V in > V tn V dsn > V gsn – V tn V out > V in - V tn V gsn > V V in > V tn V dsn < V gsn – V tn V out < V - V tn V gsn < V V in < V tn Saturated Linear Cutoff I dsn I dsp V out V DD V in V gsn = V in V dsn = V out
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This note was uploaded on 03/19/2008 for the course EE 577B taught by Professor Bhatti during the Spring '08 term at USC.

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LECTURE 4 DC AND TRANSIENT RESPONSE - Introduction to CMOS...

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