HW08

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1/4 Computer Logic Design I (CpE 100) Assignment #8 Due: Monday, Apr. 27 (in class) Problem 1. Assume that the inverter in the given circuit has a propagation delay of 5 ns and the AND gate has a propataion delay of 10 ns. Complete the following timing diagram for the circuit showing X , Y , and Z . Assume that X is initially 0, Y is initially 1, X becomes 1 for 80 ns, and then X is 0 again. Problem 2. 10 20 30 40 50 60 70 80 90 100 0 Z Y X

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2/4 Problem 3. Problem 4. Problem 5.
3/4 Problem 6. The shift register of Figure 12-10 can be made to shift to the left by adding external connections between the Q outputs and

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• Spring '18

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